5/14/20071Group IVWei-Yin ChenMyong Hyon ChoMIT 6.375 Complex Digital Systems 2007 SpringProject Goal Design and implement an out-of-ordering superscalar SMIPSv2 processorSMIPSv2 processorMIT 6.375 Complex Digital Systems 2007 SpringOutline Introduction In-Order vs. Out-of-Order Register RenamingROd i B ffMIT 6.375 Complex Digital Systems 2007 Spring Architectural Design Bluespec Implementation Results ConclusionRe-Ordering Buffer Superscalar ArchitectureIn-Order vs. Out-of-OrderLW R1, 0(R2)TIMEADD R7, R6, R5ADD R10, R9, R8MIT 6.375 Complex Digital Systems 2007 SpringADD R4, R1, R3…Out-of-Ordering(OoO) execution can increase IPC5/14/20072Register RenamingLW R2, 0(R1)ADD R3, R6, R0LW R2, 0(R1)ADD R3, R2, R1ADD R4, R3, R0MIT 6.375 Complex Digital Systems 2007 SpringADD R3, R2, R1ADD R4, R3, R0(R3 = R1 + R2)ADD R3, R6, R0(R3 = R6 + R0)Register renaming can solve this problem.Register RenamingADDI R1, R0, 1024LW R2, 0(R1)ADD R3, R2, R1ADDI P1, R0, 1024LW R2, 0(P1)ADD R3, R2, P1ADDI P1, R0, 1024LW P2, 0(P1)ADD R3, P2, P1ADDI P1, R0, 1024LW P2, 0(P1)ADD P3, P2, P1ADDI P1, R0, 1024LW P2, 0(P1)ADD P3, P2, P1ADDI P1, R0, 1024LW P2, 0(P1)ADD P3, P2, P1MIT 6.375 Complex Digital Systems 2007 SpringADD R4, R3, R0ADD R3, R6, R0R1R2R3R4Rename TableADD R4, R3, R0ADD R3, R6, R0R1P1R2R3R4R1 P1R2 P2R3P3R4ADD R4, R3, R0ADD R3, R6, R0ADD R4, P3,R0ADD R3, R6, R0R1 P1R2P2R3R4ADD P4, P3,R0ADD R3, R6, R0R1 P1R2 P2R3 P3R4P4ADD P4, P3,R0ADD P5, R6, R0R1 P1R2 P2R3 P5 P3R4 P4Re-Ordering BufferInst src1 src2 dstADD P1P2P3ADD P4P1P6MUL P7P6P6ADD P1MUL P7P1MIT 6.375 Complex Digital Systems 2007 SpringAND P5 P4 P7Re-Ordering Buffer (ROB)ALUROB keeps information for OoO dispatch.Superscalar ArchitectureInst src1 src2 dstADD P1P2P3ADD P4P1P6MUL P7P6P6ADD P1MUL P7P1ADD P4MultMIT 6.375 Complex Digital Systems 2007 SpringAND P5 P4 P7Re-Ordering Buffer (ROB)Adder5/14/20073Outline Introduction Architectural Design Main TasksPipeline StagesMIT 6.375 Complex Digital Systems 2007 Spring Bluespec Implementation Results ConclusionPipeline Stages Microarchitectural DesignMain Tasks Insertion- Fetch instructions- Rename registers- Insert into ROB Dispatch- Send ‘ready’ instructions to execution unitsUpdate- Update ROB to show values are readyMIT 6.375 Complex Digital Systems 2007 SpringMain Tasks Branch - Resolve branches- Rollback on mis-predictionsCitCommit- Finish ‘safe’ instructionsMIT 6.375 Complex Digital Systems 2007 SpringPipeline Stages ALU instructionspcGeninsertiondispatch execute update retireM ittiMIT 6.375 Complex Digital Systems 2007 SpringpcGen insertiondispatchaddrUpdateaddrdispatchrequestupdateresponseretireMemory instructionspcGen insertion dispatchbranchresolve(link pc)branchupdateretire Branches and Jumps5/14/20074Microarchitectural Design Overall DesignDecode, Rename, InsertMIT 6.375 Complex Digital Systems 2007 SpringMicroarchitectural Design Overall DesignBranchesMIT 6.375 Complex Digital Systems 2007 SpringMicroarchitectural Design Overall DesignRetire (Commit or Discard)MIT 6.375 Complex Digital Systems 2007 SpringMicroarchitectural Design Status of entries in ROBVEF1111111inst …BNE…SUB…ADDMIT 6.375 Complex Digital Systems 2007 Spring11ADD…-SUB updates value- ADD is dispatched to ALU- BNE is dispatched to branch unit5/14/20075Microarchitectural Design Status of entries in ROBVEF11101101inst …BNE…SUB…ADDMIT 6.375 Complex Digital Systems 2007 Spring01ADD…- BNE is resolved, mis-predictionMicroarchitectural Design Status of entries in ROBVEF01 10 1 101inst …BNE…SUB…ADDMIT 6.375 Complex Digital Systems 2007 Spring01ADD…- SUB is retired (discarded)- ADD cannot be retiredMicroarchitectural Design Status of entries in ROBVEF01 10 1 1011inst …BNE…SUB…ADDMIT 6.375 Complex Digital Systems 2007 Spring011ADD…- ADD gets the result from ALU- ADD is now retired (discarded)Outline Introduction Architectural Design Bluespec ImplementationBluespec Rules and MethodsMIT 6.375 Complex Digital Systems 2007 SpringBluespec Rules and Methods Rule Concurrency Design Exploration Results Conclusion5/14/20076Bluespec Rules in mkProc Insertion y discardFetchy decodeInsert Dispatchy dispatchALUy dispatchMemymemReq Actions in different stages should work at the same time Why don’t they?memReq Branchy branchResolvey branchStep2Linky branchStep2 Updatey aluUpdatey memUpdatey memUpdateNOP Retirey retireInstyyMIT 6.375 Complex Digital Systems 2007 SpringBluespec Methods in mkROB Insertion y Action insertEntryy Action insertMemEntry Dispatchy aluInstFirst / Action aluInstPopy brInstFirst / Action brInstPopy ActionValue memInstPopyActionValuememReqPop Insertion y discardFetchy decodeInsert Dispatchy dispatchALUy dispatchMemy memReqMIT 6.375 Complex Digital Systems 2007 SpringyActionValuememReqPop Branchy Action discardy Action resolve Updatey Action aluUpdResulty Action linkUpdResulty Action memUpdAddry Bool getValidBit Retirey ActionValue retirePopq Branchy branchResolvey branchStep2Linky branchStep2 Updatey aluUpdatey memUpdatey memUpdateNOP Retirey retireInst…High Method Concurrency in ROB FirstConcurrency Analysis Initial Designy A huge register containing all ROB fields and entries Read-Write Patternmethod1method1method3y Every entry is read and written by many methodsy All action methods conflicty Compiling is slowMIT 6.375 Complex Digital Systems 2007 SpringRegistermethod1method3Rule Concurrency How to get high concurrency? Every method write to RWireRulemethod2method1RWire RWirey Structural rule to handle all the cases Or Bluespec way!y Data structure separationy ROB Method ordering with EHRMIT 6.375 Complex Digital Systems 2007 SpringRegisterregAregB0regB1method2method15/14/20077Data Structure Separation Separated Data Structurebased on the number of reads and writesrdst lrdst inst taken pc+4VEFIO rsrc1prsrc2 p sid After this, compile time becomes reasonableMIT 6.375 Complex Digital Systems 2007 SpringRemained in Vector- global read - multiple writersFitted in RegFile- limited read - single writerRule Ordering in mkProc Methodology of rule ordering propagationy Determine the top rule orderingy Change the method order of all leaf gmodulesy Change the EHR index for state variablesy Keep EHR index consistent within a rule Problem: longer critical
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