Slide 1The biggest SoC driversCurrent Cellphone ArchitectureAn under appreciated factSoC Trajectory: multicores, heterogeneous, regular, ...Things to rememberCommon quotesThrough the early 1980s:… less than world classNew mind set: Design affects everything!New ways of expressing behavior to reduce design complexityReusing IP BlocksBluespec promotes composition through guarded interfacesBluespecBluespec SystemVerilog (BSV)Bluespec: State and Rules organized into modulesProgramming with rules: A simple exampleGCD in BSVGCD Hardware ModuleGCD: Another implementationBluespec Tool flowGenerated Verilog RTL: GCDGenerated HardwareGenerated Hardware ModuleGCD: A Simple Test BenchGCD: Test BenchGCD: Synthesis resultsMultiplier ExampleMultiplier in BluespecSummaryFebruary 14, 2007 L04-1http://csg.csail.mit.edu/6.375/Bluespec-1:Design methods to facilitate rapid growth of SoCsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 14, 2007L04-2http://csg.csail.mit.edu/6.375/The biggest SoC driversExplosive growth in markets forcell phones game boxessensors and actuatorsFunctionality and applications are constrained primarily by: - cost - power/energy constrainsFebruary 14, 2007L04-3http://csg.csail.mit.edu/6.375/Current Cellphone ArchitectureComms. ProcessingApplication ProcessingWLAN RFWLAN RFWLAN RFWCDMA/GSM RFToday’s chip becomes a block in tomorrow’s chipIP reuse is essentialHardware/software migrationFebruary 14, 2007L04-4http://csg.csail.mit.edu/6.375/An under appreciated factIf a functionality (e.g. H.264) is moved from a programmable device to a specialized hardware block, the power/energy savings are 100 to 1000 foldbut our mind setSoftware is forgivingHardware design is difficult, inflexible, brittle, error prone, ...Power savings more specialized hardwareFebruary 14, 2007L04-5http://csg.csail.mit.edu/6.375/SoC Trajectory:multicores, heterogeneous, regular, ...On-chip memory banksStructured on-chip networksGeneral-purpose processorsCan we rapidly produce high-quality chips and surrounding systems and software?Application-specific processing unitsIBM Cell ProcessorFebruary 14, 2007L04-6http://csg.csail.mit.edu/6.375/Things to rememberDesign costs (hardware & software) dominate Within these costs verification and validation costs dominateIP reuse is essential to prevent design-team sizes from explodingdesign cost = number of engineers x time to designFebruary 14, 2007L04-7http://csg.csail.mit.edu/6.375/Common quotes“Design is not a problem; design is easy”Almost complete reliance on post-design verification for qualityMind set“Verification is a problem”“Timing closure is a problem”“Physical design is a problem”February 14, 2007L04-8http://csg.csail.mit.edu/6.375/The U.S. auto industry Sought quality solely through post-build inspection Planned for defects and reworkand U.S. quality was…Through the early 1980s:DefectMake Inspect ReworkDefectDefectFebruary 14, 2007L04-9http://csg.csail.mit.edu/6.375/… less than world classAdding quality inspectors (“verification engineers”) and giving them better tools, was not the solutionThe Japanese auto industry showed the way“Zero defect” manufacturingFebruary 14, 2007L04-10http://csg.csail.mit.edu/6.375/New mind set:Design affects everything!A good design methodologyCan keep up with changing specsPermits architectural explorationFacilitates verification and debuggingEases changes for timing closureEases changes for physical designPromotes reuseDesign for Correctness It is essential toFebruary 14, 2007L04-11http://csg.csail.mit.edu/6.375/New ways of expressing behavior to reduce design complexity Decentralize complexity: Rule-based specifications (Guarded Atomic Actions)Lets you think one rule at a timeFormalize composition: Modules with guarded interfacesAutomatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodologyBluespec Smaller, simpler, clearer, more correct codeStrong flavor of UnityFebruary 14, 2007L04-12http://csg.csail.mit.edu/6.375/data_inpush_req_npop_req_nclkrstndata_outfullemptyReusing IP BlocksExample: Commercially available FIFO IP blockThese constraints are spread over many pages of the documentation...February 14, 2007L04-13http://csg.csail.mit.edu/6.375/Bluespec promotes compositionthrough guarded interfacesnot fullnot emptynot emptynnrdyenabrdyenabrdyenqdeqfirstFIFOtheModuleAtheModuleBtheFifo.enq(value1);theFifo.deq();value2 = theFifo.first();theFifo.enq(value3);theFifo.deq();value4 = theFifo.first();theFifoEnqueue arbitration controlDequeue arbitration controlSelf-documenting interfaces; Automatic generation of logic to eliminate conflicts in use.February 14, 2007L04-14http://csg.csail.mit.edu/6.375/BluespecWhat is it?Programming with RulesExample GCDSynthesis of circuitsAnother Example: MultiplicationBluespec is available in two versions:BSV – Bluespec in System VerilogESEPro – Bluespec in SystemCThese lectures will use BSV syntax5-minute break to stretch you legsFebruary 14, 2007L04-15http://csg.csail.mit.edu/6.375/Bluespec SystemVerilog (BSV)Power to express complex static structures and constraintsChecked by the compiler“Micro-protocols” are managed by the compilerThe necessary hardware for muxing and control is generated automatically and is correct by constructionEasier to make changes while preserving correctness Smaller, simpler, clearer, more correct code not just simulation, synthesis as wellFebruary 14, 2007L04-16http://csg.csail.mit.edu/6.375/Bluespec: State and Rules organized into modulesAll state (e.g., Registers, FIFOs, RAMs, ...) is explicit.Behavior is expressed in terms of atomic actions on the state: Rule: condition action Rules can manipulate state in other modules only via their interfaces.interfacemoduleFebruary 14, 2007L04-17http://csg.csail.mit.edu/6.375/Programming withrules: A simple exampleEuclid’s algorithm for computing the Greatest Common Divisor (GCD):15 6 9 6 subtract 3 6 subtract 6 3 swap 3 3 subtract 0 3 subtractanswer:February 14, 2007L04-18http://csg.csail.mit.edu/6.375/module mkGCD (I_GCD); Reg#(int) x <- mkRegU; Reg#(int) y <- mkReg(0); rule swap ((x > y) && (y != 0)); x <= y; y <= x; endrule rule subtract ((x <= y) && (y != 0)); y <= y – x; endrule method Action start(int a, int b) if (y==0);x <= a; y <= b; endmethod method int result() if (y==0); return x;
View Full Document
Unlocking...