GAA-to-RTL Synthesis using the Bluespec Compiler6.375 Tutorial 8February 15, 2007In this tutorial you will gain experience using the Bluespec Compiler (BSC) to automaticallysynthesize a register transfer level (RTL) hardware description from a guarded atomic action (GAA)hardware description. A GAA hardware description decomposes the design into many rules oractions. Each rule has a predicate and only fires when that predicate is true. Rules read a subset ofthe design’s state, perform some operation, and then write a subset of the design’s state. Each ruleis atomic with respect to all other rules, and as a consequence a hardware designer can considereach r ule in isolation assuming no other rules are firing in parallel. For this course we will be writingour GAA u s ing the Bluespec System Verilog (BSV) hardware d escription language. The BluespecCompiler takes BSV as input and generates an efficient RTL implementation which preserves theGAA semantics. Figure 1 shows how the Bluespec Compiler fi ts into the 6.375 toolflow.The most straightforward RTL implementation of a GAA design would simp ly execute one ru leeach cycle. Although semantically correct, th is implementation would be extremely slow. TheBluespec Compiler attempts to schedule multiple rules to fire in the same clock cycle while stillmaintaining correctness.This tutorial begins by examining a greatest common divisor unit to illustrate the basics of thecompiler and the language. The tutorial then uses several toy examples to show various s chedulingissues. Finally, a multi-cycle (unpipelined) SMIPSv2 processor is used to demonstrate designinglarger systems with Bluespec.The following documentation is located in the course locker (/mit/6.375/doc) and provides addi-tional information about the Bluespec System Verilog language as well as the Bluespec Compiler.• bsc-reference-guide.pdf - Bluespec System Verilog language reference• bsc-user-guide.pdf - Bluespec Compiler user guide• bsc-style-guide.pdf - Patterns and idioms for designing with Bluespec• bsc-timing-closure.pdf - Ap proaches for increasing performance of Bluespec designs• bsc-known-issues.pdf - Know bugs and issues with th e Bluespec Compiler• bsc-examples - Directory containing several Bluespec examplesGetting startedBefore using the 6.375 toolflow you must add th e course locker and run the course setup scrip t withthe following two commands.% add 6.375% source /mit/6.375/setup.cshFor this tutorial we w ill be examining a greatest common divisor unit and a multi-cycle (un-pipelined) SMIPSv2 processor as our example BSV designs. You should create a working directoryand checkout the examples from the course CVS repository using the following commands.6.375 Tutorial 8, Spring 2007 2TimingAreaDesign CompilerGateLevelNetlistTimingAreaLayoutGateLevelNetlistFloorPlanEncounter (FP)BSVSourceVerilogRTLBluespec CompilerVCSVirSimRTLSimEncounter (PAR)StdCellLibDesign VisionTestOutputsExecute SimFigure 1: Encounter Toolflow% mkdir tut8% cd tut8% cvs checkout examples/gcd-v% cvs checkout examples/gcd-bsv% cvs checkout examples/smipsv2-4mcycle-bsvBefore starting the tutorial, browse through the two example Bluespec projects. The actual designswill b e discussed in more detail in the following sections. Notice that the directory structure isidentical to our previous projects. The src directory contains our BSV sou rce and the builddirectory contains various makefiles and scripts for running the tools. There is a new b uild directorynamed bsc-compile for running the Bluespec Compiler.Running the Bluespec CompilerIn this s ection, we will be using the Bluespec compiler to synthesize a simple GCD un it. Take acloser look at the source code located in examples/gcd-bsv/src. The IGcd.bsv file contains aninterface for a GCD unit while the mkGcd.bsv and mkGcdWithAlu.bsv files contain two differentimplementations of this interface. It is common to keep an interface and its implementations inseparate files. The source directory also contains an appropriate test harness. The mkGcdTH m odule6.375 Tutorial 8, Spring 2007 3in the mkGcdTH.bsv BSV file implements a simple state machine which pushes several tests intothe GCD unit and verifies the results. The mkGcdTHwrapper.v file is a Verilog wrapper to drivethe clock and reset signals in our design. All of our Bluespec projects will need a toplevel Verilogwrapper.Figure 2 is a cloud diagram and Figure 3 is the corresponding Bluespec code for the mkGcd module.A cloud diagram shows the r ules, methods, and state present in the design and uses arrows toindicate the dataflow between these elements. Action-value method, action methods (such as thestart method), and rules (such as swap and subtract) are all represented with clouds since allthree constructs can change the state of a module. This is in contrast to value methods such asthe result method which cannot change the state of a module.There are a couple key syntactic issues which are important to keep in mind when writing in BSV.The first is that each BSV file should contain one and only one package, and that package shouldhave the exact same name as the file. For example, the mkGcd.bsv file contains one package namedmkGcd. At the beginning of each package we use import statements to tell the compiler whichpackages (and thus which BSV files) will be used by the cur rent package. For example, the mkGcdpackage imports the IGcd package since it contains the GCD interface. All BSV type names mustbegin with an uppercase letter and all module names must begin with a lowercase letter. Forexample, the IGcd interface, Reg#(Int#(32)) interface, and the Int#(32) type all begin with anuppercase letter, while the mkGcd module begins with a lowercase letter. Although not required, wesuggest that you us e an uppercase I prefix for all interfaces. We will use the TH suffix to indicatefiles and modules which make up a test harness.We will run the Bluespec Compiler manually and th en learn later how to automate the processwith makefiles. Begin by creating a temporary build directory and copying the BSV source files.We must copy the BSV source files since the Bluespec Compiler currently assumes that the sourcefiles are located in the same d ir ectory from which the compiler is executed.% pwdtut8% cd examples/gcd-bsv/build% mkdir temp% cd temp% cp ../../src/*.bsv .We can now use the following two commands to compile each BSV file into Verilog. You canlearn more about the possible command line
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