DOC PREVIEW
MIT 6 375 - Study Guide

This preview shows page 1-2-3-4-5-6 out of 19 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 19 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

6.375 Spring 2011Final ProjectsRichard UhlerMarch 11, 2011Final ProjectsBuild a complex digital design using FPGAIGroups of 2 to 3 studentsIGroups meet individually with Arvind, TA, Mentor weeklyduring assigned slot sometime 3-4:30pm Monday orWednesday in Arvind’s officeIWeekly reports due day before the meeting, emailed in PDFformat to [email protected] and your mentorScheduleWeek Date Deliverable0 Monday, March 14 Preliminary Proposal0 Wednesday, March 16 Project Idea Presentation1 Week of March 28 Final Proposal, High-Level Designand Test Plan2 Week of April 4 Microarchitectural Description3 Week of April 11 Implementation Status and PlannedExploration4 Week of April 18 First Synthesis Results5 Week of April 25 Simulation Demonstration6 Week of May 2 FPGA Demonstration7 Wednesday, May 11 Final Report, Final PresentationProject ConsiderationsIShould benefit from using an FPGAIHigh performance matters,ICan take advantage of high parallelism,IOr otherwise makes sense to do in hardwareIApplication should be well understoodIIs there accessible reference C code?IFor domain specific applications, you should be familiar withthe domain.IReuse of infrastructure extremely valuableIFor example, reuse SMIPS or audio pipeline, or past yearsprojects infrastructure.Project ConsiderationsIShould benefit from using an FPGAIHigh performance matters,ICan take advantage of high parallelism,IOr otherwise makes sense to do in hardwareIApplication should be well understoodIIs there accessible reference C code?IFor domain specific applications, you should be familiar withthe domain.IReuse of infrastructure extremely valuableIFor example, reuse SMIPS or audio pipeline, or past yearsprojects infrastructure.Project ConsiderationsIShould benefit from using an FPGAIHigh performance matters,ICan take advantage of high parallelism,IOr otherwise makes sense to do in hardwareIApplication should be well understoodIIs there accessible reference C code?IFor domain specific applications, you should be familiar withthe domain.IReuse of infrastructure extremely valuableIFor example, reuse SMIPS or audio pipeline, or past yearsprojects infrastructure.Past ProjectsPosted on Website under Projects2010IRay TracingIGenetic Algorithm to Discover Efficient Sorting NetworksIAdvanced Processor DesignISMIPS SIMDIHomomorphic EncryptionIMulti-Voice Audio PlaybackIPedestrian DetectionProject IdeasMulticore SMIPSIDo something interesting with a Multicore SMIPSIWe have a version with MSI cache coherence implementedyou can start from.PCinstReqQinstRespQpcGen exec writebackdataReqQdataRespQRFileStageL1 I$ L1 D$PCinstReqQinstRespQpcGen exec writebackdataReqQdataRespQRFileStageL1 I$ L1 D$PCinstReqQinstRespQpcGen exec writebackdataReqQdataRespQRFileStageL1 I$ L1 D$PCinstReqQinstRespQpcGen exec writebackdataReqQdataRespQRFileStageL1 I$ L1 D$L2 I$ L2 D$Multithreaded SMIPSIImplement an SMIPS processor that interleaves the executionof multiple threads in hardwareIYou can experiment with cores support 2-8 threadsIImplement fine-grain, coarse-grain, or simultaneousmultithreading.(http://www.realworldtech.com/page.cfm?articleid=RWT122600000000)Cache Hierarchy Exploration with SMIPSIExperiment with different types and levels of cachingITry different: associativity, inclusivity, replacement policiesOther SMIPS Project IdeasOut-of-order superscalar SMIPS ProcessorFor example, using Tomasulo’s algorithm for out-of-order executionwith register renaming through reservation stations.SMIPS DSP ExtensionsUse the SMIPS coprocessor interface to add a DSP accelerator toa basic SMIPS processor. You will need to extend the SMIPS ISAand write appropriate test/benchmark codes. Compareperformance against baseline SMIPS.Other SMIPS Project IdeasOut-of-order superscalar SMIPS ProcessorFor example, using Tomasulo’s algorithm for out-of-order executionwith register renaming through reservation stations.SMIPS DSP ExtensionsUse the SMIPS coprocessor interface to add a DSP accelerator toa basic SMIPS processor. You will need to extend the SMIPS ISAand write appropriate test/benchmark codes. Compareperformance against baseline SMIPS.Other SMIPS Project IdeasPrefetchingTry implementing a hardware prefetcher to bring values into cachebefore the processor requests them. Stream buffers are onetechnique which predicts the stride of regular accesses.Compressed Memory SystemsImplement a compressed memory system, where cache lines areuncompressed when loaded into cache, and compressed again whenevicted to main memory.Other SMIPS Project IdeasPrefetchingTry implementing a hardware prefetcher to bring values into cachebefore the processor requests them. Stream buffers are onetechnique which predicts the stride of regular accesses.Compressed Memory SystemsImplement a compressed memory system, where cache lines areuncompressed when loaded into cache, and compressed again whenevicted to main memory.Modeling On Chip NetworksIExperiment with virtual channels, arbitration in 2D Meshnetwork.IProcessor elements could be: SMIPS, Special Processors, orjust stubsHigh Quality Pitch Shifting Audio PipelineIRefactor Audio Pipelinefrom labs to work with 1024point FFT and use othertricks to make it reallysound good.(http://sethares.engr.wisc.edu/vocoders/phasevocoder.html)Generalized Sudoku SolverDesign Contest for 2009 International Conference onField-Programmable Technology(http://fpt09.cse.unsw.edu.au/competition.html)SAT SolverIGiven Boolean formula in conjunctive normal form, figure outif any assignment of variables makes the formula trueISatisfiability is NP-Complete(A ∨ B) ∧ (¬B ∨ C ∨ ¬D) ∧ (D ∨ ¬E


View Full Document

MIT 6 375 - Study Guide

Documents in this Course
IP Lookup

IP Lookup

15 pages

Verilog 1

Verilog 1

19 pages

Verilog 2

Verilog 2

23 pages

Encoding

Encoding

21 pages

Quiz

Quiz

10 pages

IP Lookup

IP Lookup

30 pages

Load more
Download Study Guide
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Study Guide and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Study Guide 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?