1February 14, 2007 L04-1http://csg.csail.mit.edu/6.375/Bluespec-1:Design methods to facilitate rapid growth of SoCsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologySystem-on-a-chipFebruary 14, 2007L04-2http://csg.csail.mit.edu/6.375/The biggest SoC driversExplosive growth in markets for cell phones game boxes sensors and actuatorsFunctionality and applications are constrained primarily by:-cost- power/energy constrains2February 14, 2007L04-3http://csg.csail.mit.edu/6.375/Current Cellphone ArchitectureComms. ProcessingApplication ProcessingWLAN RFWLAN RFWLAN RFWCDMA/GSM RFComplex, High Performancebut must not dissipate more than 3 wattsToday’s chip becomes a block in tomorrow’s chipIP reuse is essentialHardware/software migrationIP = Intellectual PropertyFebruary 14, 2007L04-4http://csg.csail.mit.edu/6.375/An under appreciated factIf a functionality (e.g. H.264) is moved from a programmable device to a specialized hardware block, the power/energy savings are 100 to 1000 foldbut our mind set Software is forgiving Hardware design is difficult, inflexible, brittle, error prone, ...Power savings ⇒ more specialized hardware3February 14, 2007L04-5http://csg.csail.mit.edu/6.375/SoC Trajectory:multicores, heterogeneous, regular, ...On-chip memory banksStructured on-chip networksGeneral-purpose processorsCan we rapidly produce high-quality chips and surrounding systems and software?Application-specific processing unitsIBM Cell ProcessorFebruary 14, 2007L04-6http://csg.csail.mit.edu/6.375/Things to rememberDesign costs (hardware & software) dominate Within these costs verification and validation costs dominateIP reuse is essential to prevent design-team sizes from explodingdesign cost = number of engineers x time to design4February 14, 2007L04-7http://csg.csail.mit.edu/6.375/Common quotes“Design is not a problem;design is easy”Almost complete reliance on post-design verification for qualityMind set“Verification is a problem”“Timing closure is a problem”“Physical design is a problem”February 14, 2007L04-8http://csg.csail.mit.edu/6.375/The U.S. auto industrySought quality solely through post-build inspectionPlanned for defects and reworkand U.S. quality was…Through the early 1980s:DefectMake Inspect ReworkDefectDefect5February 14, 2007L04-9http://csg.csail.mit.edu/6.375/… less than world classAdding quality inspectors (“verification engineers”) and giving them better tools, was not the solutionThe Japanese auto industry showed the way “Zero defect” manufacturing February 14, 2007L04-10http://csg.csail.mit.edu/6.375/New mind set:Design affects everything!A good design methodology Can keep up with changing specs Permits architectural exploration Facilitates verification and debugging Eases changes for timing closure Eases changes for physical design Promotes reuseDesign for Correctness⇒ It is essential to6February 14, 2007L04-11http://csg.csail.mit.edu/6.375/New ways of expressing behavior to reduce design complexity Decentralize complexity: Rule-based specifications (Guarded Atomic Actions) Lets you think one rule at a timeFormalize composition: Modules with guarded interfaces Automatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodologyBluespecÎ Smaller, simpler, clearer, more correct codeStrong flavor of UnityFebruary 14, 2007L04-12http://csg.csail.mit.edu/6.375/data_inpush_req_npop_req_nclkrstndata_outfullemptyReusing IP BlocksExample: Commercially available FIFO IP blockThese constraints are spread over many pages of the documentation...No machine verification of such informal constraints is feasible7February 14, 2007L04-13http://csg.csail.mit.edu/6.375/Bluespec promotes compositionthrough guarded interfacesnot fullnot emptynot emptynnrdyenabrdyenabrdyenqdeqfirstFIFOtheModuleAtheModuleBtheFifo.enq(value1);theFifo.deq();value2 = theFifo.first();theFifo.enq(value3);theFifo.deq();value4 = theFifo.first();theFifoEnqueuearbitration controlDequeuearbitration controlSelf-documenting interfaces; Automatic generation of logic to eliminate conflicts in use.February 14, 2007L04-14http://csg.csail.mit.edu/6.375/BluespecWhat is it?Programming with Rules Example GCDSynthesis of circuitsAnother Example: MultiplicationBluespec is available in two versions:BSV – Bluespec in System VerilogESEPro – Bluespec in SystemCThese lectures will use BSV syntax5-minute break to stretch you legs8February 14, 2007L04-15http://csg.csail.mit.edu/6.375/Bluespec SystemVerilog (BSV)Power to express complex static structures and constraints Checked by the compiler“Micro-protocols” are managed by the compiler The necessary hardware for muxing and control is generated automatically and is correct by constructionEasier to make changes while preserving correctnessÎ Smaller, simpler, clearer, more correct codeÎ not just simulation, synthesis as wellFebruary 14, 2007L04-16http://csg.csail.mit.edu/6.375/Bluespec: State and Rules organized into modulesAll state (e.g., Registers, FIFOs, RAMs, ...) is explicit.Behavior is expressed in terms of atomic actions on the state:Rule: condition Î actionRules can manipulate state in other modules only via their interfaces.interfacemodule9February 14, 2007L04-17http://csg.csail.mit.edu/6.375/Programming withrules: A simple exampleEuclid’s algorithm for computing the Greatest Common Divisor (GCD):15 696subtract36subtract63swap33subtract03subtractanswer:February 14, 2007L04-18http://csg.csail.mit.edu/6.375/module mkGCD (I_GCD);Reg#(int) x <- mkRegU;Reg#(int) y <- mkReg(0);rule swap ((x > y) && (y != 0));x <= y; y <= x;endrulerule subtract ((x <= y) && (y != 0));y <= y – x;endrulemethod Action start(int a, int b) if (y==0);x <= a; y <= b;endmethodmethod int result() if (y==0);return x;endmethodendmoduleInternalbehaviorGCD in BSVExternalinterfaceStatetypedef int Int#(32)Assumes x /= 0 and y /= 0xyswap sub10February 14, 2007L04-19http://csg.csail.mit.edu/6.375/rdyenabintintrdystartresultGCDmoduleinty == 0y == 0implicit conditionsinterface I_GCD;method Action start (int a, int b);method int result();endinterfaceGCD Hardware Modulet#(type t)ttt ttIn a GCD call tcould beInt#(32),UInt#(16),Int#(13), ...The module can easily be made polymorphicMany different implementations can provide the same interface: module mkGCD (I_GCD)February 14, 2007L04-20http://csg.csail.mit.edu/6.375/module mkGCD (I_GCD);Reg#(int) x <-
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