Timing Model of a Superscalar O-o-O processor in HAsim FrameworkWhat is HAsimHAsim contd.Functional PartitionModel cycle vs FPGA cycleAPorts – monitoring ticksMIPS R10-k specsTiming model designTiming Model top-level designDecode/Dispath ModuleIssue ModuleDifferences of my timing model from R-10kReasons for timing differencesSimulation resultsMiscellaneousTiming Model of a Superscalar O-o-O processor in HAsim FrameworkMurali VijayaraghavanWhat is HAsimFramework to write software-like timing models and run it on FPGAsSoftware timing models are inherently sequential – hence slowParallelism is achieved by implementing the timing model on FPGAsHAsim contd.Functional partition == ISATiming partition == micro-architectureTiming Partitionmodel time(stalls, mispredicts, etc)Functional Partitioncorrect execution(multiply, divide, etc)requestsresponsesFunctional PartitionTOKGENFETFetAlgDECDecAlgEXEExeAlgMEMMemAlgLCOLCOAlgGCOGCOAlgRegStateMemStateModel cycle vs FPGA cycleFunctional simulator can take any number of FPGA cycles for an operationSo there must be an explicit mechanism to monitor the ticks of the processor being modelledAPorts – monitoring ticksEach module in timing partition is connected with each other using APortsA clock tick conceptually begins when the module has read from every input APort and ends when it writes to every output APortBut the tick localized to each portMIPS R10-k specs64-bit processorOut-of-order executionSuperscalarFetchWidth – 4CommitWidth – 42 ALUs1 Load/Store unit1 FPUTiming model designFunctional partition operates only on one instruction at a timeBut timing model time-multiplexes multiple operations to operate on more than one instruction at a timeTiming Model top-level designFetch Free Buffer PC at MispredictPredicted PC4 TokensDecode/DispathIssue4 IssueIntQ buffer leftAddrQ buffer leftExecuteFU OpsExec ResultsCommit4 CommitToken Fetch DecodeExecMemGCOLCODecode/Dispath ModuleBranch/JR Pred ROBPredicted PC UpdateInst Buffer (8) DecodeInsert4 InstUpdate fromexecIntQ Free CountAddrQ Free Count4 issue4 CommitPC at MispredictBusy RegFileIssue ModuleIntQ (O-o-O)AddrQ (In Order)4 InstScoreBoardTo 2 ALUsTo Load StoreDifferences of my timing model from R-10kSMIPS ISA – no floating point ops32-bit registers and addressingNo delay slotOne extra cycle in branch mispredictJR and JALR has to go through the Integer QReasons for timing differencesCurrently functional partition gives only information about branches. So JR and JALR’s address can be got only after execution of JR or JALRI didn’t implement the branch cache which eliminates the extra cycle in branch mispredictSimulation resultsSimulated SMIPS v2 ADDUI test caseTook 239 FPGA cycles to simulate 7 model cycles – must look into this number as the “bottleneck” is the instruction queue, which takes 7 * 21 cycles = 147 cyclesMiscellaneousLines of code for timing model ~ 1300Compared to ~1200 for a simple SMIPS processor in Lab2, excluding
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