IntroductionProject ObjectiveOverviewEncoder OverviewDecoder OverviewPuncturing ScheduleHigh-Level Design and Test PlanInterfaceSub-modulesStatesStages and RulesCode EnumerationAdd-Compare-SelectSuggestion UpdateSpine Evaluator UpdateGet Output MessageTest PlanMicro-Architectural DesignPuncturing SchedulerSalsa Hash ModuleSalsa20 StandardExpansion FunctionsSalsa ImplementationSalsa Module InterfaceSymbol MapperSpine EvaluatorSorterBacktrack MemoryImplementation EvaluationDebuggingFPGA SynthesisCode AnalysisDesign Space ExplorationImproving Hash ModuleSpeed, Latency, ThroughputHow much better can we do?Concurrency and PipeliningFuture WorkBibliography6.375 Complex Digital Systems DesignRateless Wireless Networking with Spinal CodesFinal Project ReportMikhail Volkov, Minjie Chen, Edison AchelengwaElectrical Engineering and Computer ScienceMassachusetts Institute of TechnologyMay 11, 2011Contents1 Introduction 31.1 Project Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.1 Encoder Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.2 Decoder Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.3 Puncturing Schedule . . . . . . . . . . . . . . . . . . . . . . . . . 52 High-Level Design and Test Plan 72.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Sub-modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Stages and Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.4.1 Code Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . 92.4.2 Add-Compare-Select . . . . . . . . . . . . . . . . . . . . . . . . . 92.4.3 Suggestion Update . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4.4 Spine Evaluator Update . . . . . . . . . . . . . . . . . . . . . . . 102.4.5 Get Output Message . . . . . . . . . . . . . . . . . . . . . . . . . 102.5 Test Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Micro-Architectural Design 123.1 Puncturing Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2 Salsa Hash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.1 Salsa20 Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.2 Expansion Functions . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.3 Salsa Implementation . . . . . . . . . . . . . . . . . . . . . . . . 143.2.4 Salsa Module Interface . . . . . . . . . . . . . . . . . . . . . . . . 163.3 Symbol Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4 Spine Evaluator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5 Sorter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.6 Backtrack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Implementation Evaluation 194.1 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2 FPGA Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 Code Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Design Space Exploration 235.1 Improving Hash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2 Speed, Latency, Throughput . . . . . . . . . . . . . . . . . . . . . . . . . 235.3 How much better can we do? . . . . . . . . . . . . . . . . . . . . . . . . 255.4 Concurrency and Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . 266 Future Work 28Bibliography 291 INTRODUCTION1 Introduction1.1 Project ObjectiveThe aim of this project is to provide an implementation for a rateless wireless network-ing scheme called Cortex. This scheme was developed quite recently in MIT CSAIL[3]. Rateless networking offers performance be nefits over traditional fixed rate codingschemes. The sender encodes the data using a novel rateless spinal code which uses arandom hash function over the message bits to directly produce a sequence of constel-lation symbols for transmission. The sender and receiver use …
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