6.375: Complex Digital SystemsWhy take 6.375New, exciting and useful …Wide Variety of Products Rely on ASICsWhat’s required?Current Cellphone ArchitectureServer microprocessors also need specialized blocksReal power saving implies specialized hardwareWill multicores reduce the need for new hardware?SoC & Multicore Convergence: more application specific blocksTo reduce the design cost of SoCs we need …Hardware design today is like programming was in the fifties, i.e., before the invention of high-level languagesProgrammers had to know many detail of their computerFor designing complex SoCs deep circuits knowledge is secondaryBluespec A new way of expressing behaviorIP Reuse via parameterized modules Example OFDM based protocolsHigh-level Synthesis from BluespecFPGAs: a new opportunityChip Design StylesExponential growth: Moore’s LawIntel Penryn (2007)But Design Effort is Growing Nvidia Graphics Processing UnitsDesign Cost Impacts Chip Cost An Altera studyField-Programmable Gate Arrays (FPGAs)FPGA Pros and ConsThe new opportunityFun: Design systems that you never thought you would design in a courseSome Bluespec/FPGA projects at MITH.264 Video Decoder Chun-Chieh Lin, K Elliott Fleming [MEMOCODE 2008]AirBlue: A platform for Cross-Layer Wireless Protocol developmentIBM: PowerPC Prototype K. Ekanadham, Jessica Tseng (IBM) Asif Khan, M. Vijayaraghavan (MIT)Phase II: IBM/MIT Collaboration March 2009 –The Course PhilosophyThe course has no text book but …L01-1February 3, 2010 http://csg.csail.mit.edu/6.3756.375: Complex Digital SystemsLecturer: ArvindTA: Richard S. UhlerAdministration: Sally LeeL01-2February 3, 2010 http://csg.csail.mit.edu/6.375Why take 6.375Something new and exciting as well as usefulFun: Design systems that you never thought you could design in a coursemade possible by large FPGAs and BluespecYou will also discover that is possible to design complex digital systems with little knowledge of circuitsL01-3February 3, 2010 http://csg.csail.mit.edu/6.375New, exciting and useful …L01-4February 3, 2010 http://csg.csail.mit.edu/6.375Wide Variety of Products Rely on ASICsASIC = Application-Specific Integrated CircuitL01-5February 3, 2010 http://csg.csail.mit.edu/6.375Source: http://www.intel.com/technology/silicon/mooreslaw/index.htmWhat’s required?ICs with dramatically higher performance, optimized for applicationsand at a size and power to deliver mobility cost to address mass consumer marketsL01-6February 3, 2010 http://csg.csail.mit.edu/6.375Current Cellphone ArchitectureTwo chips, each with an ARM general-purpose processor (GPP) and a DSP (TI OMAP 2420)Comms. ProcessingApplication ProcessingWLAN RFWLAN RFWLAN RFWCDMA/GSM RFComplex, High Performancebut must not dissipate more than 3 wattsMany specialized complex blocksL01-7February 3, 2010 http://csg.csail.mit.edu/6.375Server microprocessors also need specialized blocks compression/decompressionencryption/decryptionintrusion detection and other security related solutionsDealing with spamSelf diagnosing errors and masking them…L01-8February 3, 2010 http://csg.csail.mit.edu/6.375Real power saving implies specialized hardwareH.264 video decoder implementations in software vs. hardware the power/energy savings could be 100 to 1000 foldbut our mind set is that hardware design is:Difficult, riskyIncreases time-to-market Inflexible, brittle, error prone, ...Difficult to deal with changing standards, …L01-9February 3, 2010 http://csg.csail.mit.edu/6.375Will multicores reduce the need for new hardware?64-core TileraL01-10February 3, 2010 http://csg.csail.mit.edu/6.375SoC & Multicore Convergence:more application specific blocksOn-chip memory banksStructured on-chip networksGeneral-purpose processorsApplication-specific processing unitsL01-11February 3, 2010 http://csg.csail.mit.edu/6.375To reduce the design cost of SoCs we need … Extreme IP reuseMultiple instantiations of a block for different performance and application requirements Packaging of IP so that the blocks can be assembled easily to build a large system (black box model)Architectural exploration to understand cost, power and performance tradeoffsFull system simulations for validation and verification “Intellectual Property”L01-12February 3, 2010 http://csg.csail.mit.edu/6.375Hardware design today is like programming was in the fifties, i.e., before the invention of high-level languagesL01-13February 3, 2010 http://csg.csail.mit.edu/6.375Programmers had to know many detail of their computerAn IBM 650 Instruction: 60 1234 1009•“Load the contents of location 1234 into the distribution; put it also into the upper accumulator; set lower accumulator to zero; and then go to location 1009 for the next instruction.”IBM 650(1954)L01-14February 3, 2010 http://csg.csail.mit.edu/6.375For designing complex SoCs deep circuits knowledge is secondary Using modern high-level hardware synthesis tools like Bluespec requires computer science training in programming and architecture rather than circuit designL01-15February 3, 2010 http://csg.csail.mit.edu/6.375Bluespec A new way of expressing behaviorA formal method of composing modules with parallel interfaces (ports) Compiler manages muxing of ports and associated controlPowerful and zero-cost parameterization of modulesEncapsulation of C and Verilog codes using Bluespec wrappers Helps Transaction Level modeling Smaller, simpler, clearer, more correct code not just simulation, synthesis as wellBluespecL01-16February 3, 2010 http://csg.csail.mit.edu/6.375IP Reuse via parameterized modulesExample OFDM based protocolsMACMACstandard specificpotential reuseScramblerFECEncoderInterleaver MapperPilot &GuardInsertionIFFTCPInsertionDe-ScramblerFECDecoderDe-InterleaverDe-MapperChannelEstimaterFFT SynchronizerTXControllerRXControllerS/PD/AA/DDifferent algorithmsDifferent throughput requirementsReusable algorithm with different parameter settings(Alfred) Man Cheuk Ng, …L01-17February 3, 2010 http://csg.csail.mit.edu/6.375High-level Synthesis from BluespecVCD outputDebussyVisualizationCBluesimCycleAccurateBluespec SystemVerilog sourceVerilog 95 RTLVerilog simBluespec CompilerRTL synthesisgatesFPGAPower estimation toolPower estimation toolL01-18February 3, 2010 http://csg.csail.mit.edu/6.375FPGAs: a new opportunityL01-19February 3, 2010 http://csg.csail.mit.edu/6.375Chip Design StylesCustom and Semi-CustomHand-drawn transistors (+ some standard
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