L12-Projects.pdfAsifMuraliElliottAlfredPellauerJaeLeeMarch 2, 2009 L12-1http://csg.csail.mit.edu/6.3756.375 Final ProjectMarch 2, 2009L12-2http://csg.csail.mit.edu/6.375GuidelinesIdeally – groups of two to threeGoal: A complex digital design –functional on FPGAs, useful, substantial Ideas related to your research domain welcomePast projects online – http://csg.csail.mit.edu/6.375/6_375_2008_www/projects.html http://csg.csail.mit.edu/6.375/6_375_2007_www/projects.html http://csg.csail.mit.edu/6.375/6_375_2006_www/projects.html http://csg.csail.mit.edu/6.884/projects.htmlMarch 2, 2009L12-3http://csg.csail.mit.edu/6.375Project ScheduleWeekly project meetings and deadlinesIntermediate reports due according to following schedule:May 14May 13May 06Apr 29Apr 22Apr 08April 01Mar 16DateProject PresentationFPGA DemonstrationSimulation DemonstrationRoutable ImplementationDetailed MicroarchitectureHigh-level Design & ArchTaskProject ReportDesign exploration plan & SRPerf expectations, tuning & SRSynthesis report (SR)Testing planFinal proposal with diagramPreliminary proposalReportMarch 2, 2009L12-4http://csg.csail.mit.edu/6.375Project ideasFloating point Unit & other processor accelerators Asif Khan, Murali VijayaraghavanSHA-3: Hash algorithm evaluation Elliott FlemingChannel Estimation Alfred Man Cheuk NgHAsim: Cycle-accurate performance modeling Michael PellauerDRAM controller Jae Lee1Status of the PowerPC Project• Single-threaded PowerPC pipeline optimized for FPGA implementation• It can execute sample code at 125MHz• It has a FIFO memory interface that connects it to the DDR2 memory controller• It also has a PLB slave interface for gathering statisticsFloating Point Unit• PowerPC FPU coded in Bluespec for FPGA implementation• Simple FIFO input, output interface – <operation type, source operand values> provided at input, <destination operand values> expected at output after a specified number of cycles• Operations are outlined in the PowerPC ISA Book 1• Primary goals are minimizing FPGA resource utilization and maximizing clock frequency• Parameterization is also desired2Reference Material• PowerPC User Instruction Set Architecture Book I Version 2.01provides all the details of the floating point processor, available upon request• http://grouper.ieee.org/groups/754/links to related papers, publically available software implementations and test rigs• http://www.opencores.com/projects.cgi/web/fpu100/overviewopen-source VHDL 32-bit FPU implementation• Floating Point TrailblazeVerilog 64-bit FPU implementation from UT Austin’s TRIPS project, available upon request1Crypto-engineSymmetric-key cryptography• Block ciphers• Encryption:f(key, msg) -> c• Decryption:f-1(key, c) -> msg• Standard used currently is AES(128, 192, 256 bits)• Reference: http://www.csrc.nist.gov/publications/fips/fips197/fips-197.pdf2Public-key cryptography• Encryption:f(public key, msg) -> c• Decryption:g(private key, c) -> msg• Example: RSA (1024 bits or more )• Referencehttp://people.csail.mit.edu/rivest/Rsapaper.pdfCrypto-engine Interfaces• AES:method Action setKey(key)method c encrypt(msg, size)method msg decrypt(c, size)• RSA:method Action setPrivateKey(private key)method Action setPublicKey(public key)method c encrypt(msg, size)method msg decrypt(c, size)• Or similar interfaces if you want to implement different crypto algorithms (including hashing)SHA-3 ProjectsSHA-3 – new standard hash functions Influence the international standard process>40 propsals, few HW implementationsMany based on existing crypto/hash functions – pick a fewSome more exotic – pick one FFT Matrix multiplicationMarch 12, 2008 L14-1http://csg.csail.mit.edu/6.3756/6/20082General ArchitectureNIOSIIBus MasterFunction Unit:MD6 EngineAvalon BusRAMBus Slave16.375 Project Idea: Channel EstimatorImpact of Channel Frequency Response2Pilot for Channel EstimationTimeCarriersTimeCarriers• Comb Type:–Part of the sub-carriers are always reserved as pilot for each symbol• Block Type:–All sub-carriers is used as pilot in a specific period• 802.11a/g use bothPossible Parameterizations• No. subcarriers• Values and locations of pilots• Locations of guard bands (unused subcarriers)All the above parameterizations are preferred to be dynamic if possible!3References[1] www.freescale.com/files/dsp/doc/app_note/AN3059.pdf[2] www.winlab.rutgers.edu/~spasojev/courses/projects/CE_OFDM.ppt1Rapid Processor Rapid Processor Simulation Using Simulation Using HAsimHAsimMichael PellauerMichael [email protected]@csail.mit.eduFPGAsFPGAs: Stand: Stand--Alone Alone vsvsAcceleratorAcceleratorStand-alone FPGA (like 6.375):Accelerator FPGA (like GPU):USBFPGAPCIeCPU2The The HAsimHAsimSimulatorSimulatorOS DriverPhysicalPlatformVirtual PlatformVirtualPlatformControllerControllerSoftwareSimulatorHardwareSimulatorCPU FPGAPCIeFunctionalPartitionTimingPartitionYou write thisProject IdeasProject IdeasExisting Timing ModelsUnpipelined (Multicore)5-stage inorder pipeline (Multicore)Out-of-order superscalarProposed idea: SMT ProcessorsSymmetric Multi-ThreadedEach core would have to track model state for multiple threadsPerform architectural exploration using SPEC benchmarks3Any Questions?Any [email protected] Access SchedulingJae Lee6.375 Complex Digital SystemsMarch 2, 2009Memory Access SchedulingProcessorcoreI$D$SDRAMcontrollerwithmemoryaccessschedulerscheduling policy,DRAM timing constraintsSDRAMSDRAMSDRAMSDRAMoff-chip memory bus• Memory access scheduling: reorder memory accesses to maximize DRAM throughput and reduce latency by exploiting multiple banks and row buffers.* S. Rixner, et. al, Memory Access Scheduling, In ISCA ’00.23D Structure of DRAM Chip• Memory data location: (bank,row,column)• Three steps in accessing the memory data:– bank precharge– row access (row activation)– column access* The figure taken from: S. Rixner, et. al, Memory Access Scheduling, in ISCA ’00. 4DRAM Bank Operation*Row BufferAccess Address (Row 0, Column 0)Row decoderColumn decoderRow address 0Column address 0DataRow 0EmptyAccess Address (Row 0, Column 1)Column address 1Access Address (Row 0, Column 9)Column address 9Access Address (Row 1, Column 0)HITHITRow address 1Row 1Column address 0CONFLICT !ColumnsRows* This slide was taken from a presentation of Prof. Onur Mutlu at CMU [MICRO ’07]. A row-conflict memory access takes
View Full Document
Unlocking...