1Modeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyMarch 1, 2010 http://csg.csail.mit.edu/6.375 L08-1Instruction settypedef enum {R0;R1;R2;…;R31} RName;typedef union tagged{struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName value; RName addr;} Store} Instr deriving(Bits, Eq);March 1, 2010http://csg.csail.mit.edu/6.375An instruction set can be implemented using many different microarchitecturestypedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;L08-22Deriving Bitstypedef struct { … } Fooderiving(Bits);To store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack)Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit deriving(Bits);type (simple concatenation of bit representations of components)It is possible to customize the pack/unpack operations to any specific desired representationMarch 1, 2010http://csg.csail.mit.edu/6.375 L08-3Tagged Unions: Bit Representationtypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct{RName cond; RName addr;} Bz;00 dst src1 src201 cond addrstruct{RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);March 1, 2010http://csg.csail.mit.edu/6.37510 dst addr11 dst immAutomatically derived representation; can be customized by the user written pack and unpack functionsL08-43The PlanNon-pipelined processor⇐Nonpipelined processor⇐Two-stage Inelastic pipelineTwo-stage Elastic pipeline –next Two-stage Elastic pipeline –next lectureMarch 1, 2010http://csg.csail.mit.edu/6.375Some understanding of simple processor pipelines is needed to follow this lectureL08-5Non-pipelined ProcessorpcrfCPUfetch & execute iMem dMemmodule mkCPU#(Mem iMem, Mem dMem)();Reg#(Iaddress) pc <- mkReg(0);March 1, 2010http://csg.csail.mit.edu/6.375RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1;rule fetch_Execute ...endmoduleL08-64Non-pipelined processor rulerule fetch_Execute (True);case (instr) matchestaggedAdd {dst:.rd,src1:.ra,src2:.rb}: beginrf.upd(rd, rf[ra]+rf[rb]);pc <= predIaendtagged Bz {cond:.rc,addr:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; endtagged Load {dest:.rd,addr:.ra}: beginrf.upd(rd, dMem.read(rf[ra]));pc <= predIa;my syntaxrf[r] ≡ rf.sub(r)March 1, 2010http://csg.csail.mit.edu/6.375endtagged Store {value:.rv,addr:.ra}: begindMem.write(rf[ra],rf[rv]);pc <= predIa;endendcaseendruleAssume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cycleL08-7Register FileHow many read ports?How many write ports?Concurrency properties?March 1, 2010L08-8http://csg.csail.mit.edu/6.3755The PlanNon-pipelined processorNonpipelined processorTwo-stage Inelastic pipeline ⇐Two-stage Elastic pipelineTwo-stage Elastic pipelineMarch 1, 2010http://csg.csail.mit.edu/6.375 L08-9Two-stage InelasticPipelinefetch & decodeexecutebuRegpc rf dMembuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5Actions to be performed in parallel every cycle:Fetch Action: Decodes the instruction at the current pc March 1, 2010http://csg.csail.mit.edu/6.375Fetch Action: Decodes the instruction at the current pc and fetches operands from the register file and stores the result in buReg Execute Action: Performs the action specified in buReg and updates the processor state (pc, rf, dMem)L08-10rule InelasticPipeline2(True);fetchAction; executeAction; endrule6Instructions & TemplatesbuReg contains instruction templates, i.e., decoded instructionstypedef union taggedtypedef union tagged {struct {RName dst; RName src1; RName src2} Add;struct {RName cond; RName addr} Bz;struct {RName dst; RName addr} Load;struct {RName value; RName addr} Store;} Instr deriving(Bits, Eq);March 1, 2010http://csg.csail.mit.edu/6.375typedef union tagged { struct {RName dst; Value op1; Value op2} EAdd;struct {Value cond; Iaddress tAddr} EBz;struct {RName dst; Daddress addr} ELoad;struct {Value value; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);L08-11Fetch & Decode ActionFills the buReg with a decoded instructionbuReg <= newIt(instr); function InstrTemplate newIt(Instr instr);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}:return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]};tagged Bz {cond:.rc,addr:.addr}:return EBz{cond:rf[rc],addr:rf[addr]};taggedLoad {dst:.rd,addr:.addr}:March 1, 2010http://csg.csail.mit.edu/6.375taggedLoad {dst:.rd,addr:.addr}:return ELoad{dst:rd,addr:rf[addr]};tagged Store{value:.v,addr:.addr}:return EStore{value:rf[v],addr:rf[addr]};endcase endfunction L08-127Execute Action: Reads buRegand modifies state (rf,dMem,pc)case (buReg) matches tagged EAdd{dst:.rd,src1:.va,src2:.vb}: bif d(d +b)begin rf.upd(rd, va+vb); pc <= predIa; end tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); pc <= predIa; endtagged EStore{value:.vv,addr:.av}: begin dMem.write(av, vv); pc <= predIa; endMarch 1, 2010http://csg.csail.mit.edu/6.375tagged EBz {cond:.cv,addr:.av}:if (cv != 0) then pc <= predIa;else begin pc <= av; Invalidate buRegendendcaseWhat does this mean?L08-13Issues with buRegfetch & decodeexecutebuRegpc rf dMembuRegbuReg may not always contain an instruction. Why? start cycle Execute stage may kill the fetched instructions because of branch mispredictionMarch 1, 2010http://csg.csail.mit.edu/6.375Can’t update buReg in two concurrent actionsfetchAction; executeActionL08-148InelasticPipelinefirst attemptfetch & decodeexecutepcrfCPUbuRegrule SyncTwoStage (True);letinstr=iMem read(pc);letinstr= iMem.read(pc); let predIa = pc+1;Action fetchAction = actionbuReg <= Valid newIt(instr);pc <= predIa;endaction;March 1, 2010http://csg.csail.mit.edu/6.375case (buReg) matches each instruction execution calls fetchActionor puts Invalid in buReg …endcaseendcase endruleL08-15Executecase (buReg) matches taggedValid it:fetch & decodeexecutepcrfCPUbuRegtaggedValid .it: case (it) matchestagged EAdd{dst:.rd,src1:.va,src2:.vb}:
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