Modular RefinementSuccessive refinement & Modular StructureArchitectural refinementsTwo-stage PipelineProperties Required of Register File and FIFO for Instruction PipeliningBypass Register FileOne Element Searchable Pipeline SFIFOSuppose we used the wrong SFIFO?bu.find < bu.deqCPU as one moduleA Modular organizationInterface definitions: Fetch and ExecuteRecursive modular organizationIssueSyntax for Recursive ModulesPassing parametersFetch ModuleExecute ModuleExecute Module RuleSubtle Architecture IssuesModular refinement: Separating Fetch and DecodeFetch Module Refinement Separating Fetch and DecodeFetch Module RefinementModular refinement: Replace magic memory by multicycle memoryThe desired behaviorAction Connectives: Par vs. SeqPredicating Actions: Guards vs. IfsSplitting the rulePassing data from Fetch to DecodeMethods of Fetch moduleMulticycle memory: Refined Execute Module RuleSplitting the Backend Rules: The execute ruleSplitting the Backend Rules The writeback ruleFinal stepSlide 34Modular Refinement Arvind Computer Science & Artificial Intelligence LabMassachusetts Institute of Technologyhttp://csg.csail.mit.edu/6.375March 8, 2010 L10-1Successive refinement & Modular Structurefetchexecute iMemrfCPUdecodememorypcwrite-backdMemCan we derive the 5-stage pipeline by successive refinement of a 2-stage pipeline?fetch & decodeexecutepcrfCPUbuhttp://csg.csail.mit.edu/6.375March 8, 2010 L10-2Architectural refinementsSeparating Fetch and DecodeReplace magic memory by multicycle memoryMulticycle functional units …http://csg.csail.mit.edu/6.375First, let us examine our two-stage pipelineMarch 8, 2010 L10-3Two-stage Pipelinerule fetch_and_decode (!stallfunc(instr, bu)); bu.enq(newIt(instr,rf)); pc <= predIa;endrulerule execAdd (it matches tagged EAdd{dst:.rd,src1:.va,src2:.vb}); rf.upd(rd, va+vb); bu.deq(); endrulerule BzTaken(it matches tagged Bz {cond:.cv,addr:.av}) &&& (cv == 0); pc <= av; bu.clear(); endrule rule BzNotTaken(it matches tagged Bz {cond:.cv,addr:.av}); &&& !(cv == 0); bu.deq(); endrulerule execLoad(it matches tagged ELoad{dst:.rd,addr:.av}); rf.upd(rd, dMem.read(av)); bu.deq(); endrulerule execStore(it matches tagged EStore{value:.vv,addr:.av}); dMem.write(av, vv); bu.deq(); endrulefetch & decodeexecutepcrfCPUbufetch rule can execute concurrently with every execute rule except the BzTaken ruleXhttp://csg.csail.mit.edu/6.375March 8, 2010 L10-4Properties Required of Register File and FIFO for Instruction PipeliningBypass Register File: rf.upd(r1, v) < rf.sub(r2)Pipeline SFIFO bu: {first , deq} < {find, enq} bu.first < bu.find bu.first < bu.enqbu.deq < bu.findbu.deq < bu.enqhttp://csg.csail.mit.edu/6.375March 8, 2010 L10-5Bypass Register Filemodule mkBypassRFFull(RegFile#(RName,Value)); RegFile#(RName,Value) rf <- mkRegFileFullWCF(); RWire#(Tuple2#(RName,Value)) rw <- mkRWire(); method Action upd (RName r, Value d); rf.upd(r,d); rw.wset(tuple2(r,d)); endmethod method Value sub(RName r); case rw.wget() matches tagged Valid {.wr,.d}: return (wr==r) ? d : rf.sub(r); tagged Invalid: return rf.sub(r); endcase endmethodendmodule“Config reg file”http://csg.csail.mit.edu/6.375March 8, 2010 L10-6One Element Searchable Pipeline SFIFOmodule mkSFIFO1#(function Bool findf(tr r, t x)) (SFIFO#(t,tr)); Reg#(t) data <- mkRegU(); Reg#(Bool) full <- mkConfigReg(False); RWire#(void) deqEN <- mkRWire(); Bool deqp = isValid (deqEN.wget())); method Action enq(t x) if (!full || deqp); full <= True; data <= x; endmethod method Action deq() if (full); full <= False; deqEN.wset(?); endmethod method t first() if (full); return (data); endmethod method Action clear(); full <= False; endmethod method Bool find(tr r); return (findf(r, data) && full); endmethod endmodule bu.enq > bu.deqbu.enq > bu.firstbu.enq < bu.clear(full && !deqp));bu.find < bu.enqbu.find < bu.deqbu.find < bu.clear bu.deq > bu.firstbu.deq < bu.clearhttp://csg.csail.mit.edu/6.375bu.find < bu.enqbu.find > bu.deqbu.find < bu.clear March 8, 2010 L10-7Suppose we used the wrong SFIFO?bu.find < bu.deqhttp://csg.csail.mit.edu/6.375Will the system produce wrong results?NO because the fetch rule will simply conflict with the execute rules March 8, 2010 L10-8CPU as one modulehttp://csg.csail.mit.edu/6.375Read method callAction method callMethod calls embody both data and control (i.e., protocol)iMemdMemfetch & decodepcexecuteRFile rfSFIFO buCPUMarch 8, 2010 L10-9A Modular organizationSuppose we include rf and pc in Fetch and bu in ExecuteFetch delivers decoded instructions to Execute and needs to consult Execute for the stall conditionExecute writes back data in rf and supplies the pc value in case of a branch mispredictioniMemRFile rfFIFO budMemfetch & decodepcexecutesetPcCPUenqIt WBstallmodules call each other (recursive)http://csg.csail.mit.edu/6.375March 8, 2010 L10-10Interface definitions:Fetch and Executeinterface Fetch; method Action setPC (Iaddress cpc); method Action writeback (RName dst, Value v); endinterfaceinterface Execute; method Action enqIt(InstTemplate it); method Bool stall(Instr instr)endinterfacehttp://csg.csail.mit.edu/6.375March 8, 2010 L10-11Recursive modular organizationmodule mkCPU2#(Mem iMem, Mem dMem)(); Execute execute <- mkExecute(dMem, fetch); Fetch fetch <- mkFetch(iMem, execute);endmodulerecursive callsUnfortunately, the recursive module syntax is not so simplehttp://csg.csail.mit.edu/6.375March 8, 2010 L10-12IssueA recursive call structure can be wrong in the sense of “circular calls”; fortunately the compiler can perform this checkUnfortunately recursive call structure amongst modules is supported by the compiler in a limited way.The syntax is complicatedRecursive modules cannot be synthesized separatelyhttp://csg.csail.mit.edu/6.375March 8, 2010 L10-13Syntax for Recursive Modules moduleFix is like the Y combinator F = Y Fmodule mkFix#(Tuple2#(Fetch, Execute) fe)(Tuple2#(Fetch, Execute)); match{.f, .e} = fe; Fetch fetch <- mkFetch(e); Execute execute <- mkExecute(f); return(tuple2(fetch,execute));endmodule (* synthesize *)module mkCPU(Empty); match {.fetch, .execute} <- moduleFix(mkFix);endmodulehttp://csg.csail.mit.edu/6.375March 8, 2010 L10-14Passing parametersmodule mkCPU#(IMem iMem, DMem dMem)(Empty); module mkFix#(Tuple2#(Fetch, Execute) fe)(Tuple2#(Fetch, Execute)); match{.f, .e} = fe; Fetch fetch <-
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