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MIT 6 375 - Lecture Notes

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IP Lookup

IP Lookup

15 pages

Verilog 1

Verilog 1

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Verilog 2

Verilog 2

23 pages

Encoding

Encoding

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Quiz

10 pages

IP Lookup

IP Lookup

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1Stmt FSMArvind (with the help of Nirav Dave) Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyMarch 10, 2010L11-1http://csg.csail.mit.edu/6.375gyMotivationSome common design patterns are tdi t i BSVtedious to express in BSV Testbenchs Sequential machines (FSMs)especially sequential looping structuresespecially sequential looping structuresThese are tedious to express in Verilog as well (but not in C)March 10, 2010L11-2http://csg.csail.mit.edu/6.3752Testing the IP Lookup DesigneultoutQcbufyesgetTokenInput: IP AddressOutput: Route Valuedone?RAMfifoentergetResucbufyesnoNeed to test many different input/output sequencesMarch 10, 2010L11-3http://csg.csail.mit.edu/6.375Testing IP LookupCall many streams of requests Call many streams of requests responses from the device under test (DUT)Case 1dut enter(17 23 12 225)Case 2dut enter(128 30 90 124)Check correct with 1 request at a timeCheck correct with 2 concurrent requestsdut.enter(17.23.12.225)dut.getResult()dut.enter(17.23.12.25)dut.getResult()dut.enter(128.30.90.124)dut.enter(128.30.90.126)dut.getResult()dut.getResult()March 10, 2010L11-4http://csg.csail.mit.edu/6.3753But we usually want morecounters, display, ...function Action makeReq(x);actionreqCnt <= reqCnt + 1;reqCnt <= reqCnt + 1;dut.enter(x);$display(“[Req #: ”,fshow(reqCnt),“] = ”,fshow(x));endactionendfunctionfunction Action getResp();action resCnt <= resCnt + 1;let x <- dut.getResult();$display(“[Rsp #:”,fshow(resCnt),“] = ”,fshow(x));endactionendfunction March 10, 2010L11-5http://csg.csail.mit.edu/6.375Writing a Testbench (Case 1)rule step0(pos==0);rule step2(pos==2);k R (17 23 12 25)makeReq(17.23.12.225);pos <= 1;endrulerule step1(pos==1);getResp();pos <= 2;makeReq(17.23.12.25);pos <= 3;endrulerule step3(pos==3);getResp();pos <= 4;endruleWait until endrulerule finish(pos==4);$finish;endruleresponse is readyMarch 10, 2010L11-6http://csg.csail.mit.edu/6.3754A more complicated Case:Initializing memoryf(i)nIiaddr0Need an FSM in HW as l d int i; Addr addr=addr0;bool done = False;for(i=0; i<nI; i++){mem.write(addr++,f(i));}done = True;Cmemory can only do one write per cycleReg#(int) i <-mkReg(0);Reg#(Addr) addr <-mkReg(addr0);Reg#(Bool) done <-mkReg(False);BSVg#( )g( );rule initialize (i < nI);mem.write (addr, f(i));addr <= addr + 1;i <= i + 1;if (i+1 == nI) done<=True;endruleMarch 10, 2010L11-7http://csg.csail.mit.edu/6.375Initialize a memory with a 2-D patternReg#(int) i <-mkReg(0);Reg#(int) j <-mkReg(0);nJjaddr0Reg#(int) j <mkReg(0);Reg#(Addr) addr <-mkReg(addr0);Reg#(Bool) done <-mkReg(False);rule loop ((i < nI) && (j < nJ));mem.write (addr, f(i,j));addr <= addr + 1;if (j < nJ-1)j <= j + 1;f(i,j)nIiBluespec code gets messier as compared to C even with small changes in C, e.g.,else beginj <= 0;if (i < nI-1) i <= i + 1;else done <= True;endendrule initialization based on old memory values initialization has to be done more than onceMarch 10, 2010L11-8http://csg.csail.mit.edu/6.3755An imperative viewvoid doTest(){makeReq(17.23.12.225);It is easy to write a sequence in CqgetResp();makeReq(17.23.12.25);getResp();exit(0);}seqsequence in CWriting this in rules is tedious:Can we just write the actions and have the makeReq(17.23.12.225);getResp();makeReq(17.23.12.25);getResp();$finish();endseq;actions and have the compiler make the rules?March 10, 2010L11-9http://csg.csail.mit.edu/6.375From Action Lists to FSMsStmt sstartFSM interfaceinterface FSM;method Action start();method Bool done();endinterfacedoneCreating an FSMendinterfacemodule mkFSM#(Stmt s)(FSM);March 10, 2010L11-10http://csg.csail.mit.edu/6.3756The Stmt SublanguageStmt =<Bluespec Action>| seq s1..sN endseq| par s1..sN endpar| if-then / if-then-else| for-, while-, repeat(n)-(w/ break and continues)March 10, 2010L11-11http://csg.csail.mit.edu/6.375Translation Example: Seq to FSMStmt s = seqmakeReq(17.23.12.225);module mkFSM_s(FSM)Reg#(Bit#(3)) pos <- mkReg(0);rule step1(pos==1);makeReq(17.23.12.225); pos <= 2;getResp();makeReq(17.23.12.25);getResp();$finish();endseq;FSM fkFSM( )qpendrulerule step2(pos==2);getResp(); pos <= 3; endrulerule step3(pos==3);makeReq(17.23.12.25); pos <= 4;endrulerule step4(pos==4);getResp(); pos <= 5; endrulerule step5(pos==5);FSM f <- mkFSM(s);$finish; pos <= 0; endrulemethod Action start() if(pos==0);pos <= 1; endmethodmethod Bool done()return (pos == 0);endmethodendmoduleMarch 10, 2010L11-12http://csg.csail.mit.edu/6.3757Parallel TasksseqrefReq(x);We want to check dutand ref have q();refRes(rReg);dutReq(x);dutRes(dReg);checkMatch(rReg,dReg);endseqdutand ref have same result Do each, then check resultsBut it doesn’t matter that ref finishes before dut starts…March 10, 2010L11-13http://csg.csail.mit.edu/6.375Start ref and dut at the same timeSeq. for each seq qimplementationStart togetherBoth run at own parseq refReq(x);refRes(refv);endseqseq dutReq(x);dutRes(dutv); endseqrate Wait until both are doneendparcheckMatch(refv,dutv);endseqMarch 10, 2010L11-14http://csg.csail.mit.edu/6.3758What exactly is the translation?The Stmt sublanguage is clearer The Stmt sublanguage is clearer for the designer; but, what FSM do we get?Let’s examine each Stmt Construction case and see how it Construction case and see how it can be implementedMarch 10, 2010L11-15http://csg.csail.mit.edu/6.375Base Case: Primitive Action: aReg#(Bool) doneR <- mkReg(True);rule dowork(!doneR); a; doneR <= True;endrulemethod Action start() if (doneR);doneR <= False;endmethodmethod Bool done(); return doneR; endmethodMarch 10, 2010L11-16http://csg.csail.mit.edu/6.3759Sequential List - seq seq s1...sN endseq: sequential composition#Reg#(int) s <-mkReg(0);FSM s1 <- mkFSM (s1); … ; FSM sN <- mkFSM (sN); Bool flag = rule one (s==1); s1.start(); s <= 2; endrulerule two (s==2&& s1.done()); s2.start(); s <= 3; endrule…rule n (s==n && sN-1 done());s1.done() && … sN.done();rule n (s==n && sN1.done());sN.start(); s <= 0; endrulemethod Action start() if (flag); s <= 1; endmethodmethod Bool done(); return flag; endmethodMarch 10, 2010L11-17http://csg.csail.mit.edu/6.375Implementation - parpar s1...sN endpar: parallel compositionFSM s1 <- mkFSM (s1); … ; FSM sN <- mkFSM (sN); Bool flag =method Action start() if (flag);s1.start(); s2.start(); …; sN.start();endmethodmethodBooldone(); returnflag;endmethods1.done() && … && sN.done();method Booldone(); return flag; endmethodMarch 10,


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