Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37February 8, 2008 L02-1http://csg.csail.mit.edu/6.375/Verilog 1 - Fundamentals6.375 Complex Digital SystemsArvindFebruary 8, 2007FAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleFebruary 8, 2008L02-2http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleFebruary 8, 2008L02-3http://csg.csail.mit.edu/6.375/Originally designers used breadboards for prototypingNumber of Gatesin Design10102103104105106107Solderless BreadboardPrinted circuit board tangentsoft.net/elec/breadboard.htmlhome.cogeco.caNo symbolic execution or testingFebruary 8, 2008L02-4http://csg.csail.mit.edu/6.375/HDLs enabled logic level simulation and testingGate Level DescriptionManualTestResultsSimulateNumber of Gatesin Design10102103104105106107HDL = Hardware Description LanguageFebruary 8, 2008L02-5http://csg.csail.mit.edu/6.375/Designers began to use HDLs for higher level designGate LevelNumber of Gatesin Design10102103104105106107HDL models offered “precise” & executable specification but the translation between the levels remained manualBehavioralAlgorithmTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateManualFebruary 8, 2008L02-6http://csg.csail.mit.edu/6.375/HDLs led to tools for automatic translationGate LevelNumber of Gatesin Design10102103104105106107HDLs: Verilog, VHDL… Tools: Spice, ModelSim, DesignCompiler, …BehavioralAlgorithmTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateManualLogic SynthesisAuto Place + RouteFebruary 8, 2008L02-7http://csg.csail.mit.edu/6.375/Raising the abstraction further …Gate LevelNumber of Gatesin Design10102103104105106107Bluespec and associated toolsGuarded AtomicActionsTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateGAA CompilerLogic SynthesisAuto Place + RouteFebruary 8, 2008L02-8http://csg.csail.mit.edu/6.375/The current situation BehavioralLevelRegisterTransfer LevelGate LevelLogic SynthesisBluespecStructural RTLVerilog, VHDL, SystemVerilogC, C++, SystemCBehavioral RTLVerilog, VHDL, SystemVerilogMATLABSimulators and other tools are available at all levels but not compilers from the behavioral level to RTLFebruary 8, 2008L02-9http://csg.csail.mit.edu/6.375/Common misconceptionsBehavioral Languages = CRTL languages are necessarily lower-level than behavioral languagesYes- in the sense that C or SystemC is farther away from hardwareNo- in the sense that HDLs can incorporate the most advanced language ideas.Bluespec is a modern high-level language and at the same time can describe hardware to the same level of precision as RTLFebruary 8, 2008L02-10http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleFebruary 8, 2008L02-11http://csg.csail.mit.edu/6.375/Bit-vector is the only data type in VerilogHigh impedance, floatingZUnknown logic valueXLogic one1Logic zero0MeaningValueAn X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality.A bit can take on one of four valuesFebruary 8, 2008L02-12http://csg.csail.mit.edu/6.375/“wire” is used to denote a hardware netwire [15:0] instruction;wire [15:0] memory_req;wire [ 7:0] small_net; instructionmemory_reqinstructionsmall_net?Absolutely no type safety when connecting nets!February 8, 2008L02-13http://csg.csail.mit.edu/6.375/Bit literalsBinary literals8’b0000_00008’b0xx0_1xx1Hexadecimal literals32’h0a34_def116’haxxxDecimal literals32’d424’b10_11Underscores are ignoredBase format(d,b,o,h)Decimal number representing size in bitsWe’ll learn how to actually assign literals to nets a little laterFebruary 8, 2008L02-14http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleFebruary 8, 2008L02-15http://csg.csail.mit.edu/6.375/A Verilog module has a name and a port listadderA Bsumcoutmodule adder( A, B, cout, sum ); input [3:0] A; input [3:0] B; output cout; output [3:0] sum; // HDL modeling of // adder functionalityendmodule Note the semicolon at the end of the port list!Ports must have a direction (or be bidirectional) and a bitwidth4 44February 8, 2008L02-16http://csg.csail.mit.edu/6.375/Traditional Verilog-1995 Syntaxmodule adder( A, B, cout, sum ); input [3:0] A; input [3:0] B; output cout; output [3:0] sum;ANSI C Style Verilog-2001 Syntaxmodule adder( input [3:0] A, input [3:0] B, output cout, output [3:0] sum );Alternate syntaxadderA Bsumcout4 44February 8, 2008L02-17http://csg.csail.mit.edu/6.375/A module can instantiate other modulesadderA BScoutFAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( ... ); FA fa1( ... ); FA fa2( ... ); FA fa3( ... );endmodule module FA( input a, b, cin output cout, sum ); // HDL modeling of 1 bit // full adder functionalityendmodule FAbaccincoutFebruary 8, 2008L02-18http://csg.csail.mit.edu/6.375/Connecting modulesadderA BScoutFAFA FA FAmodule adder( input [3:0]
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