1February 23, 2009 http://csg.csail.mit.edu/6.375 L09-1Modular RefinementArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 23, 2009 L09-2http://csg.csail.mit.edu/6.375Successive refinement & Modular StructurefetchexecuteiMemrfCPUdecodememorypcwrite-backdMemCan we derive the 5-stage pipeline by successive refinement of a 2-stage pipeline?fetch & decodeexecutepcrfCPUbu2February 23, 2009 L09-3http://csg.csail.mit.edu/6.375A 2-Stage Processor in RTL1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Identify Input/Output ports4) Design the Controller (FSM)PC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybufControllerFebruary 23, 2009 L09-4http://csg.csail.mit.edu/6.375Designing a 2-Stage Processor with GAAPC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybuf>1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Define Interface methods: read, action, action value3February 23, 2009 L09-5http://csg.csail.mit.edu/6.375CPU as one moduleRead method callAction method callMethod calls embody both data and control (i.e., protocol)iMemdMemfetch & decodepcexecuteRFile rfFIFO buCPUFebruary 23, 2009 L09-6http://csg.csail.mit.edu/6.375CPU as one module module mkCPU#(Mem iMem, Mem dMem)();// Instantiating state elementsReg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Value) rf<- mkBypassRF();SFIFO#(InstTemplate, RName) bu<- mkSLoopyFifo(findf); // Some definitionsInstr instr = iMem.read(pc); Iaddress predIa = pc + 1;// Rulesrule fetch_decode ...rule execute ...endmoduleyou have seen this before4February 23, 2009 L09-7http://csg.csail.mit.edu/6.375A Modular organizationiMemRFile rfFIFO budMemfetch & decodepcexecutesetPcCPU-enqItWBstallSuppose we include rf and pc in Fetch and bu in ExecuteFetch delivers decoded instructions to Execute and needs to consult Execute for the stall conditionExecute writes back data in rf and supplies the pc value in case of a branch mispredictionmodules call each other (recursive)February 23, 2009 L09-8http://csg.csail.mit.edu/6.375Recursive modular organizationmodule mkCPU2#(Mem iMem, Mem dMem)();Execute execute <- mkExecute(dMem, fetch);Fetch fetch <- mkFetch(iMem, execute);endmoduleinterface Fetch;method Action setPC (Iaddress cpc);method Action writeback (RName dst, Value v); endinterfaceinterface Execute;method Action enqIt(InstTemplate it);method Bool stall(Instr instr)endinterfacerecursive callsUnfortunately, recursive module syntax is not as simple5February 23, 2009 L09-9http://csg.csail.mit.edu/6.375IssueA recursive call structure can be wrong in the sense of “circular calls”; fortunately the compiler can perform this checkUnfortunately recursive call structure amongst modules is supported by the compiler in a limited way. The syntax is complicated Recursive modules cannot be synthesized separatelyFebruary 23, 2009 L09-10http://csg.csail.mit.edu/6.375Syntax for Recursive ModulesmoduleFix is like the Y combinatorF = Y Fmodule mkFix#(Tuple2#(Fetch, Execute) fe)(Tuple2#(Fetch, Execute));match{.f, .e} = fe;Fetch fetch <- mkFetch(e);Execute execute <- mkExecute(f);return(tuple2(fetch,execute));endmodule(* synthesize *)module mkCPU(Empty);match {.fetch, .execute} <- moduleFix(mkFix);endmodule6February 23, 2009 L09-11http://csg.csail.mit.edu/6.375Passing parametersmodule mkCPU#(IMem iMem, DMem dMem)(Empty);module mkFix#(Tuple2#(Fetch, Execute) fe)w (Tuple2#(Fetch, Execute));match{.f, .e} = fe;Fetch fetch <- mkFetch(iMem,e);Execute execute <- mkExecute(dMem,f);return(tuple2(fetch,execute);wendmodulematch {.fetch, .execute} <- moduleFix(mkFix);endmoduleFebruary 23, 2009 L09-12http://csg.csail.mit.edu/6.375Fetch Modulemodule mkFetch#(IMem iMem, Execute execute) (Fetch);Instr instr = iMem.read(pc);Iaddress predIa = pc + 1;Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkBypassRegFile();rule fetch_and_decode (!execute.stall(instr)); execute.enqIt(newIt(instr,rf));pc <= predIa;endrulemethod Action writeback(RName rd, Value v);rf.upd(rd,v);endmethodmethod Action setPC(Iaddress newPC);pc <= newPC;endmethodendmodule7February 23, 2009 L09-13http://csg.csail.mit.edu/6.375Execute Modulemodule mkExecute#(DMem dMem, Fetch fetch) (Execute);SFIFO#(InstTemplate) bu <- mkSLoopyFifo(findf);InstTemplate it = bu.first;rule execute …method Action enqIt(InstTemplate it);bu.enq(it);endmethodmethod Bool stall(Instr instr);return (stallFunc(instr, bu));endmethodendmoduleFebruary 23, 2009 L09-14http://csg.csail.mit.edu/6.375Execute Module Rulerule execute (True);case (it) matchestagged EAdd{dst:.rd,src1:.va,src2:.vb}: beginfetch.writeback(rd, va+vb); bu.deq();end tagged EBz {cond:.cv,addr:.av}:if (cv == 0) then beginfetch.setPC(av); bu.clear(); endelse bu.deq();tagged ELoad{dst:.rd,addr:.av}: beginfetch.writeback(rd, dMem.read(av)); bu.deq();endtagged EStore{value:.vv,addr:.av}: begindMem.write(av, vv); bu.deq();endendcaseendrule8February 23, 2009 L09-15http://csg.csail.mit.edu/6.375Subtle Architecture Issuesinterface Fetch;method Action setPC (Iaddress cpc);method Action writeback (RName dst, Value v); endinterfaceinterface Execute;method Action enqIt(InstTemplate it);method Bool stall(Instr instr)endinterfaceAfter setPC is called the next instruction enqueued via enqIt must correspond to iMem(cpc)stall and writeback methods are closely related; writeback affects the results of subsequent stalls the effect of writeback must be reflected immediately in the decoded instructions Any modular refinement must preserve these extra linguistic semantic propertiesFebruary 23, 2009 L09-16http://csg.csail.mit.edu/6.375Fetch Module RefinementSeparating Fetch and Decodemodule mkFetch#(IMem iMem, Execute execute) (Fetch);FIFO#(Instr) fetchDecodeQ <- mkLoopyFIFO();Instr instr = iMem.read(pc);Iaddress predIa = pc + 1;…rule fetch(True);pc <= predIa;fetchDecodeQ.enq(instr);endrulerule decode (!execute.stall(fetchDecodeQ.first())); execute.enqIt(newIt(fetchDecodeQ.first(),rf));fetchDecodeQ.deq();endrulemethod Action setPC …method Action writeback …endmoduleAre any changes needed in the methods?9February 23, 2009 L09-17http://csg.csail.mit.edu/6.375Fetch Module Refinementmodule mkFetch#(IMem iMem, Execute execute) (Fetch);FIFO#(Instr) fetchDecodeQ <- mkFIFO();…Instr instr = iMem.read(pc);Iaddress predIa = pc + 1;method Action writeback(RName rd, Value v);rf.upd(rd,v);endmethodmethod Action setPC(Iaddress newPC);pc <=
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