Slide 1Successive refinement & Modular StructureA 2-Stage Processor in RTLDesigning a 2-Stage Processor with GAAOutlineCPU as one moduleCPU as one moduleFetch & Decode RuleThe Stall FunctionThe findf functionExecute RuleTransformation for PerformanceAfter RenamingSlide 14A Modular organization: recursive modulesRecursive modular organizationFetch ModuleExecute ModuleExecute Module RuleIssueConnectable MethodsConnectable OrganizationStep 1: Break up Rules only one recursive method call per rule …Step 2: Change a rule to a methodStep 2: Merging multiple rules into one method not always easyStep-1 is not always possible: Jump&Link instructionUsing RWiresJump&Link using RWires steps 1 & 2Jump&Link Connectable Version step 3My recommendationModular StructureFebruary 26, 2007 http://csg.csail.mit.edu/6.375/ L09-1Bluespec-6: Modules and InterfacesArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 26, 2007 L09-2http://csg.csail.mit.edu/6.375/Successive refinement & Modular Structurefetchexecute iMemrfCPUdecodememorypcwrite-backdMemCan we derive the 5-stage pipeline by successive refinement of a 2-stage pipeline?fetch & decodeexecutepcrfCPUbuDave, Pellauer, ArvindFebruary 26, 2007 L09-3http://csg.csail.mit.edu/6.375/A 2-Stage Processor in RTL1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Identify Input/Output ports4) Design the Controller (FSM)PC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybufmodule regfile ( input [4:0] wa, //address for write port input [31:0] wd, //write data input we, //write enable (active high) input [4:0] ra1, //address for read port 1 output [31:0] rd1, //read data for port 1 ...ControllerFebruary 26, 2007 L09-4http://csg.csail.mit.edu/6.375/Designing a 2-Stage Processor with GAAPC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybuf>setPC(new_pc)setPC(new_pc)enqNextInst(dec_inst)enqNextInst(dec_inst)update(addr,val)update(addr,val)read(addr)read(addr)interface RegisterFile#(addr_T, data_T); data_T read(addr_T); Action update(addr_T, data_T);endinterface;1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Define Interface methods: read, action, action valueFebruary 26, 2007 L09-5http://csg.csail.mit.edu/6.375/OutlineSingle module structurePerformance issueModular structure issuesFebruary 26, 2007 L09-6http://csg.csail.mit.edu/6.375/CPU as one moduleRead method callAction method callMethod calls embody both data and control (i.e., protocol)iMemdMemfetch & decodepcexecuteRFile rfFIFO buCPUFebruary 26, 2007 L09-7http://csg.csail.mit.edu/6.375/CPU as one module module mkCPU#(Mem iMem, Mem dMem)();// Instantiating state elements Reg#(Iaddress) pc <- mkReg(0); RegFile#(RName, Value) rf <- mkRegFileFull();SFIFO#(InstTemplate, RName) bu <- mkSFifo(findf);// Some definitionsInstr instr = iMem.read(pc); Iaddress predIa = pc + 1;// Rules rule fetch_decode ... rule execute ...endmoduleyou have seen this beforeFebruary 26, 2007 L09-8http://csg.csail.mit.edu/6.375/Fetch & Decode Rule rule fetch_and_decode (!stallfunc(instr, bu)); bu.enq(newIt(instr,rf)); pc <= predIa;endrule function InstrTemplate newIt(Instr instr, RegFile#(RName, Value) rf); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]}; tagged Bz {cond:.rc,addr:.addr}: return EBz{cond:rf[rc],addr:rf[addr]}; tagged Load {dst:.rd,addr:.addr}: return ELoad{dst:rd,addr:rf[addr]}; tagged Store{value:.v,addr:.addr}: return EStore{value:rf[v],addr:rf[addr]}; endcaseendfunctionyou have seen this beforeFebruary 26, 2007 L09-9http://csg.csail.mit.edu/6.375/The Stall Functionfunction Bool stallfunc (Instr instr, SFIFO#(InstTemplate, RName) bu); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: return (bu.find(ra) || bu.find(rb)); tagged Bz {cond:.rc,addr:.addr}: return (bu.find(rc) || bu.find(addr)); tagged Load {dst:.rd,addr:.addr}: return (bu.find(addr)); tagged Store {value:.v,addr:.addr}: return (bu.find(v)) || bu.find(addr)); endcaseendfunctionyou have seen this beforeFebruary 26, 2007 L09-10http://csg.csail.mit.edu/6.375/The findf functionfunction Bool findf (RName r, InstrTemplate it); case (it) matches tagged EAdd{dst:.rd,op1:.ra,op2:.rb}: return (r == rd); tagged EBz {cond:.c,addr:.a}: return (False); tagged ELoad{dst:.rd,addr:.a}: return (r == rd); tagged EStore{value:.v,addr:.a}: return (False); endcaseendfunctionSFIFO#(InstrTemplate, RName) bu <- mkSFifo(findf);mkSFifo is parameterized by the search function!you have seen this beforeFebruary 26, 2007 L09-11http://csg.csail.mit.edu/6.375/Execute Rulerule execute (True); case (it) matches tagged EAdd{dst:.rd,src1:.va,src2:.vb}: begin rf.upd(rd, va+vb); bu.deq(); end tagged EBz {cond:.cv,addr:.av}: if (cv == 0) then beginpc <= av; bu.clear(); end else bu.deq(); tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); bu.deq(); end tagged EStore{value:.vv,addr:.av}: begin dMem.write(av, vv); bu.deq(); end endcaseendruleyou have seen this beforeFebruary 26, 2007 L09-12http://csg.csail.mit.edu/6.375/Transformation for Performancerule fetch_and_decode (!stallfunc(instr, bu)1); bu.enq1(newIt(instr,rf)); pc <= predIa;endrulerule execute (True); case (it) matches tagged EAdd{dst:.rd,src1:.va,src2:.vb}: begin rf.upd0(rd, va+vb); bu.deq0(); end tagged EBz {cond:.cv,addr:.av}: if (cv == 0) then beginpc <= av; bu.clear0(); end else bu.deq0(); tagged ELoad{dst:.rd,addr:.av}: begin rf.upd0(rd, dMem.read(av)); bu.deq0(); end tagged EStore{value:.vv,addr:.av}: begin dMem.write(av, vv); bu.deq0(); end endcase endruleexecute < fetch_and_decode rf.upd0 < rf.sub1bu.first0 < {bu.deq0, bu.clear0} < bu.find1 < bu.enq1February 26, 2007 L09-13http://csg.csail.mit.edu/6.375/After RenamingThings will workboth rules can fire concurrentlyProgrammer Specifies:Rexecute < RfetchCompiler Derives:(first0, deq0) < (find1, deq1)What if the programmer wrote this?Rexecute < Rexecute < Rfetch < RfetchFebruary 26, 2007 L09-14http://csg.csail.mit.edu/6.375/OutlineSingle module structureModular structure issuesFebruary 26, 2007 L09-15http://csg.csail.mit.edu/6.375/A Modular organization: recursive modulesiMemRFile rfFIFO budMemfetch & decodepcexecutesetPcCPUModules call each other -
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