Introduction to the Altera SOPC BuilderUsing Verilog DesignThis tutorial presents an introduction to Altera’s SOPC Builder software, which is used to implement a systemthat uses the Nios II processor on an Altera FPGA device. The system development flow is illustrated by givingstep-by-step instructions for using the SOPC Builder in conjuction with the QuartusRII software to implement asimple system.The last step in the development process involves configuring the designed circuit in an actual FPGA device,and running an application program. To show how this is done, it is assumed that the user has access to the AlteraDE2 Development and Education board connected to a computer that has Quartus II and NiosRII softwareinstalled.The screen captures in the tutorial were obtained using the Quartus II version 8.0; if other versions of thesoftware are used, some of the images may be slightly different.Contents:Nios II SystemAltera’s SOPC BuilderIntegration of the Nios II System into a Quartus II ProjectRunning the Application Program1Altera’s Nios II is a soft processor, defined in a hardware description language, which can be implementedin Altera’s FPGA devices by using the QuartusRII CAD system. To implement a useful system it is necessaryto add other funcional units such as memories, input/output interfaces, timers, and communications interfaces.To facilitate the implementation of such systems, it is useful to have computer-aided-design (CAD) software forimplementing a system-on-a-programmable-chip (SOPC). Altera’s SOPC Builder is the software needed for thistask.This tutorial provides a basic introduction to Altera’s SOPC Builder, which will allow the reader to quicklyimplement a simple Nios II system on the Altera DE2 board. For a fuller treatment of the SOPC Builder, thereader can consult the Nios II Hardware Development Tutorial. A complete description of the SOPC Builder canbe found in the Quartus II Handbook Volume 4: SOPC Builder. These documents are available on the Altera website.1 Nios II SystemA Nios II system can be implemented on the DE2 board as shown in Figure 1.On-chipmemoryinterfaceSDRAMinterfaceFlashmemoryParallel I/OinterfaceSerial I/OinterfaceSRAMinterfaceSRAMchipSDRAMchipchipFlashmemoryAvalon switch fabricNios II processorJTAG UARTinterfaceUSB-BlasterinterfaceHost computerlinesParallelI/O portlinesSerialI/O portCyclone IIFPGA chipJTAG DebugmoduleFigure 1. A Nios II system implemented on the DE2 board.2The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are implementedin the Cyclone II FPGA chip. These components are interconnected by means of the interconnection networkcalled the Avalon Switch Fabric. The memory blocks in the Cyclone II device can be used to provide an on-chipmemory for the Nios II processor. The SRAM, SDRAM and Flash memory chips on the DE2 board are accessedthrough the appropriate interfaces. Parallel and serial input/output interfaces provide typical I/O ports used incomputer systems. A special JTAG UART interface is used to connect to the circuitry that provides a UniversalSerial Bus (USB) link to the host computer to which the DE2 board is connected. This circuitry and the associatedsoftware is called the USB-Blaster. Another module, called the JTAG Debug module, is provided to allow the hostcomputer to control the Nios II system. It makes it possible to perform operations such as downloading programsinto memory, starting and stopping execution, setting breakpoints, and collecting real-time execution trace data.Since all parts of the Nios II system implemented on the FPGA chip are defined by using a hardware descrip-tion language, a knowledgeable user could write such code to implement any part of the system. This would bean onnerous and time consuming task. Instead, one can use the SOPC Builder to implement a desired systemsimply by choosing the required components and specifying the parameters needed to make each component fitthe overall requirements of the system. In this tutorial, we will illustrate the capability of the SOPC Builder bydesigning a very simple system. The same approach is used to design large systems.On-chipmemoryparallel inputinterfaceparallel outputinterfaceAvalon switch fabricNios II processorJTAG UARTinterfaceUSB-BlasterinterfaceHost computerCyclone IIFPGA chipSW7 SW0 LEDG7 LEDG0Reset_n ClockLEDsJTAG DebugmoduleSwitchesFigure 2. A simple example of a Nios II system.3Our example system is given in Figure 2. The system realizes a trivial task. Eight toggle switches on the DE2board, SW 7 − 0, are used to turn on or off the eight green LEDs, LEDG7 − 0. The switches are connected to theNios II system by means of a parallel I/O interface configured to act as an input port. The LEDs are driven by thesignals from another parallel I/O interface configured to act as an output port. To achieve the desired operation, theeight-bit pattern corresponding to the state of the switches has to be sent to the output port to activate the LEDs.This will be done by having the Nios II processor execute a program stored in the on-chip memory. Continuousoperation is required, such that as the switches are toggled the lights change accordingly.We will use the SOPC Builder to design the hardware depicted in Figure 2. Next, we will assign the Cyclone IIpins to realize the connections between the parallel interfaces and the switches and LEDs which act as I/O devices.Then, we will configure the FPGA to implement the designed system. Finally, we will use the software tool calledthe Nios II Monitor Program to assemble, download and execute a Nios II program that performs the desired task.Doing this tutorial, the reader will learn about:• Using the SOPC Builder to design a Nios II-based system• Integrating the designed Nios II system into a Quartus II project• Implementing the designed system on the DE2 board• Running an application program on the Nios II processor2 Altera’s SOPC BuilderThe SOPC Builder is a tool used in conjuction with the Quartus II CAD software. It allows the user to easilycreate a system based on the Nios II processor, by simply selecting the desired functional units and specifyingtheir parameters. To implement the system in Figure 2, we have to instantiate the following functional units:• Nios II processor, which is referred to as a Central Processing Unit (CPU)• On-chip memory, which consists of the memory blocks in the Cyclone II chip; we will
View Full Document
Unlocking...