MIT 6 375 - Advanced Processor Design (33 pages)

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Advanced Processor Design



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Advanced Processor Design

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Pages:
33
School:
Massachusetts Institute of Technology
Course:
6 375 - Complex Digital Systems
Complex Digital Systems Documents

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Massachusetts Institute of Technology 6 375 Complex Digital Systems 2010 Spring Advanced Processor Design Group III Michael Eskowitz James Haupt Advisor Muralidaran Vijayaraghavan Eskowitz Haupt Page 1 Table of Contents 1 Abstract 3 2 Introduction 4 3 Basic CPU Design 4 4 Advanced Processor Implementation 6 4 1 PCGen 8 4 2 InstCounter 8 4 3 Branch Predictor 9 4 4 Decode 13 4 5 Scoreboard 14 4 6 Exec 15 4 7 BExec 17 4 8 MExec 18 4 9 Counter4 18 4 10 Writeback Stage 19 4 11 Multi Write Register File Implementation 20 5 Results 21 6 Conclusion 23 7 Future Work 24 8 7 1 Scheduling Algorithm Details 24 7 2 Scheduling Algorithm Analysis 27 7 3 Application of Scheduling System for 3 Exec Modules 28 7 4 Hardware Details 30 Bibliography 32 Eskowitz Haupt Page 2 Table of Figures Figure 3 1 Lab5 SMIPS Processor 5 Figure 3 2 Lab 5 Performance Metrics 5 Figure 4 1 Superscalar Processor Implementation 6 Figure 4 2 Branch Instruction Life cycle 10 Figure 4 3 1 bit Branch Predictor Accuracy 10 Figure 4 4 1 bit Branch Predictor State Transition Diagram 11 Figure 4 5 2 bit Branch Predictor State Transition Diagram 11 Figure 4 6 2 bit Branch Predictor Accuracy 12 Figure 4 7 Tournament 2 bit Branch Predictor State Transition Diagram 12 Figure 4 8 Tournament 2 bit Branch Predictor Accuracy 13 Figure 4 9 Conceptual Representation of Decode Permutation Stage 13 Figure 4 10 Intra Module Result Sharing Architecture 14 Figure 5 1 Summary of Benchmark IPCs 21 Figure 5 2 Comparison between issuing 2 or 1 instructions at a time 22 Figure 5 3 Resource Utilization 22 Figure 7 1 Expanding Execution Network 25 Figure 7 2 Probability of being able to schedule an instruction with two registers current in system 27 Figure 7 3 Potential Future Design Revision 30 Figure 7 4 Long Term Architectural Goal 31 Eskowitz Haupt Page 3 1 Abstract In this project we designed and implemented an in order superscalar SMIPSv2 processor on a Xilinx Virtex 5 FPGA using Bluespec System Verilog The somewhat novel



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