March 15, 2006 http://csg.csail.mit.edu/6.375/ L14-1Bluespec-8: Modules and InterfacesArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyMarch 15, 2006 L14-2http://csg.csail.mit.edu/6.375/Successive refinement & Modular StructurefetchexecuteiMemrfCPUdecodememorypcwrite-backdMemCan we derive the 5-stage pipeline by successive refinement of a 2-stage pipeline?fetch & decodeexecutepcrfCPUbuDave, Pellauer, ArvindMarch 15, 2006 L14-3http://csg.csail.mit.edu/6.375/A 2-Stage Processor in RTL1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Identify Input/Output ports4) Design the Controller (FSM)PC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybufmodule regfile (input [4:0] wa, //address for write portinput [31:0] wd, //write datainput we, //write enable (active high)input [4:0] ra1, //address for read port 1output [31:0] rd1, //read data for port 1...ControllerMarch 15, 2006 L14-4http://csg.csail.mit.edu/6.375/Designing a 2-Stage Processor with GAAPC +4InstuctionMemoryALUDecodeRegisterFileDataMemorybuf>setPC(new_pc)setPC(new_pc)enqNextInst(dec_inst)enqNextInst(dec_inst)update(addr,val)update(addr,val)read(addr)read(addr)interface RegisterFile#(addr_T, data_T);data_T read(addr_T);Action update(addr_T, data_T);endinterface;1) Design Microarchitecture2) Locate Datapaths/Memories and create modules3) Define Interface methods: read, action, action valueMarch 15, 2006 L14-5http://csg.csail.mit.edu/6.375/OutlineSingle module structure Performance issueModular structure issuesMarch 15, 2006 L14-6http://csg.csail.mit.edu/6.375/Instuctions & Templatestypedef union tagged { struct {RName dst; Value op1; Value op2} EAdd;struct {Value cond; Iaddress tAddr} EBz;struct {RName dst; Daddress addr} ELoad;struct {Value data; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);typedef union tagged {struct {RName dst; RName src1; RName src2} Add;struct {RName cond; RName addr} Bz;struct {RName dst; RName addr} Load;struct {RName value; RName addr} Store;} Inst deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;you have seen this beforeMarch 15, 2006 L14-7http://csg.csail.mit.edu/6.375/CPU as one moduleRead method callAction method callMethod calls embody both data and control (i.e., protocol)iMemdMemfetch & decodepcexecuteRFile rfFIFO buCPUMarch 15, 2006 L14-8http://csg.csail.mit.edu/6.375/CPU as one module module mkCPU#(Mem iMem, Mem dMem)();// Instantiating state elementsReg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Value) rf<- mkRegFileFull();SFIFO#(InstTemplate, RName) bu<- mkSFifo(findf);// Some definitionsInstr instr = iMem.read(pc); Iaddress predIa = pc + 1;// Rulesrule fetch_decode ...rule execute ...endmoduleyou have seen this beforeMarch 15, 2006 L14-9http://csg.csail.mit.edu/6.375/Fetch & Decode Rulerule fetch_and_decode (!stallfunc(instr, bu)); bu.enq(newIt(instr,rf));pc <= predIa;endrulefunction InstrTemplate newIt(Instr instr, RegFile#(RName, Value) rf);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}:return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]};tagged Bz {cond:.rc,addr:.addr}:return EBz{cond:rf[rc],addr:rf[addr]};tagged Load {dst:.rd,addr:.addr}:return ELoad{dst:rd,addr:rf[addr]};tagged Store{value:.v,addr:.addr}:return EStore{value:rf[v],addr:rf[addr]};endcaseendfunctionyou have seen this beforeMarch 15, 2006 L14-10http://csg.csail.mit.edu/6.375/The Stall Functionfunction Bool stallfunc (Instr instr, SFIFO#(InstTemplate, RName) bu); case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: return (bu.find(ra) || bu.find(rb));tagged Bz {cond:.rc,addr:.addr}: return (bu.find(rc) || bu.find(addr));tagged Load {dst:.rd,addr:.addr}: return (bu.find(addr));tagged Store {value:.v,addr:.addr}: return (bu.find(v)) || bu.find(addr));endcaseendfunctionyou have seen this beforeMarch 15, 2006 L14-11http://csg.csail.mit.edu/6.375/The findf functionfunction Bool findf (RName r, InstrTemplate it); case (it) matchestagged EAdd{dst:.rd,op1:.ra,op2:.rb}: return (r == rd); tagged EBz {cond:.c,addr:.a}: return (False);tagged ELoad{dst:.rd,addr:.a}: return (r == rd);tagged EStore{value:.v,addr:.a}: return (False);endcaseendfunctionSFIFO#(InstrTemplate, RName) bu <- mkSFifo(findf);mkSFifo is parameterized by the search function!you have seen this beforeMarch 15, 2006 L14-12http://csg.csail.mit.edu/6.375/Execute Rulerule execute (True);case (it) matchestagged EAdd{dst:.rd,src1:.va,src2:.vb}: beginrf.upd(rd, va+vb); bu.deq();end tagged EBz {cond:.cv,addr:.av}:if (cv == 0) then beginpc <= av; bu.clear(); end else bu.deq();tagged ELoad{dst:.rd,addr:.av}: beginrf.upd(rd, dMem.read(av)); bu.deq();endtagged EStore{value:.vv,addr:.av}: begindMem.write(av, vv); bu.deq();endendcaseendruleyou have seen this beforeMarch 15, 2006 L14-13http://csg.csail.mit.edu/6.375/Transformation for Performancerule fetch_and_decode (!stallfunc(instr, bu)1); bu.enq1(newIt(instr,rf));pc <= predIa;endrulerule execute (True);case (it) matchestagged EAdd{dst:.rd,src1:.va,src2:.vb}: beginrf.upd0(rd, va+vb); bu.deq0(); endtagged EBz {cond:.cv,addr:.av}:if (cv == 0) then beginpc <= av; bu.clear0(); end else bu.deq0();tagged ELoad{dst:.rd,addr:.av}: beginrf.upd0(rd, dMem.read(av)); bu.deq0(); endtagged EStore{value:.vv,addr:.av}: begindMem.write(av, vv); bu.deq0(); endendcase endruleexecute < fetch_and_decodeÎ rf.upd0< rf.sub1bu.first0< {bu.deq0, bu.clear0} < bu.find1< bu.enq1March 15, 2006 L14-14http://csg.csail.mit.edu/6.375/After RenamingThings will work both rules can fire concurrentlyProgrammer Specifies:Rexecute< RfetchCompiler Derives:(first0, deq0) < (find1, deq1)What if the programmer wrote this?Rexecute< Rexecute< Rfetch< RfetchMarch 15, 2006 L14-15http://csg.csail.mit.edu/6.375/OutlineSingle module structureModular structure issuesMarch 15, 2006 L14-16http://csg.csail.mit.edu/6.375/A Modular organization: recursive modulesiMemRFile rfFIFO budMemfetch & decodepcexecutesetPcCPUModules call each other-bu part of Execute- rf and pc part of Fetch&Decode- fetch delivers decoded instructions to ExecuteenqItWBstallMarch 15, 2006 L14-17http://csg.csail.mit.edu/6.375/Recursive modular organizationmodule mkCPU2#(Mem iMem, Mem dMem)();Execute execute <- mkExecute(dMem, fetch);Fetch fetch <- mkFetch(iMem, execute);endmoduleinterface Fetch;method Action setPC (Iaddress cpc);method Action writeback (RName dst, Value v);
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