Importing IP into SOPC Builder6.375 Tutorial 13March 5, 2009Although SOPC Builder offers many pre-existing cores from which powerful systems may be built,designers often need to add custom IP into a system to probide some custom functionality. In thistutorial, you will learn how to import a custom block into SOPC Builder and connect it to anexisting system.Getting startedBefore using the 6.375 toolflow you must add the course locker and run the course setup script withthe following two commands.% add 6.375% source /mit/6.375/setup.cshFor this tutorial, we will be using a simple SRAM as our example design. You should create aworking directory and checkout the SRAM example project from the course CVS repository usingthe following commands.% mkdir tut13% cd tut13% cvs checkout examples/sram% cd examples/sramBefore starting, take a look at the subdirectories in the sram project directory. Figure ?? shows thesystem diagram which is implemented by the example code. The important feature in the designis the Avalon Bus Slave, which serves as a kind of glue logic to connect our SRAM to the rest ofthe system. The slave logic will translate requests and responses from our SRAM into signals onthe bus.Examine the directory structure of sram. The src directory contains the various Bluespec sourcesneeded for the SRAM, and the test directory contains a small test harness. The source code willbe built in the build directory.We will first compile the example Bluespec code down to Verilog, and then we will import thegenerated Verilog into SOPC builder. It is also possible to import synthesized gate-level descriptionsinto SPOC builder. To build the verilog, execute:% pwdtut13/examples/sram% cd build% make avalonmasterslavetesterThis command will build both the SRAM verilog (build/vdir/mkSmallAvalonRegisterFile.v)and the testbench. You can verify that the code built properly by running the testbench:6.375 Tutorial 13, Spring 2009 2% ./avalonmasterslavetesterPASSWe will now import mkSmallAvalonRegisterFile into SOPC builder.Importing Verilog into SOPC BuilderSOPC builder requires a Quartus II Project in order to run. Using the steps in Tutorial 10, createa new Quartus project. Open SOPC builder using the Tools → SOPC Builder menu option. Thiswill bring up the SOPC Builder user interface, which will ask you to name the new project. Givea name and click Continue.Before we start using SOPC Builder, we must first point it at the Altera IP repository. Open theTools → Options menu. Add /mit/6.375/tools/altera/altera to the I P Search Path and clickFinish. As you add IP to SOPC Builder, you will need to extend the search path.Open the Component Editor using the File → New Component button. Make note of the intro-ductory screen and then click Next, bringing up the HDL import tab. Click on Add and selectmkSmallAvalonRegisterFile.v. The wizard will think for a little bit and then given a few warn-ings and errors. These are normal and will be addressed on the subsequent tabs. Your screenshould look like this:Figure 1: HDL ScreenClick Next, bringing up the Signals tab. In this tab we will declare special groups of wires in ourdesign. mkSmallAvalonRegisterFile has a clock input and an avalon slave interface. Use theInterface column to add a new Clock Input interface and a new Avalon Memory Mapped Slave.Take a look at the other options in the Interface column menu. The most important option, whoseusage is not obvious, is new Conduit, which exports a wire to the top level of the SOPC design.6.375 Tutorial 13, Spring 2009 3This enables you to tie the wire to external pins or other non-SOPC produced hardware. Assignthe mkSmallAvalonRegisterFile signals to the appropriate Signal Types. When you are done,your Component Editor should look like this:Figure 2: Signal ScreenClick Next, bringing up the Interfaces tab. First, click the Remove Interfaces With No Signalsbutton to clean up any interfaces that SOPC builder has erroneously inferred. Associate theavalon slave with the clock sink. SOPC uses this information to ensure that communicatinginterfaces are properly clocked. Set Max pending read transactions to 1. In principal, we couldset this value to be 2, since we have some buffering capacity in the AvalonSlave module, butwe will be conservative. Click Next again and then click Finish. Congradulations, you have justimported a module. You should be able to see the mkSmallAvalonRegisterFile module in theSystem Contents Menu, and you can now use it in any SOPC designs. To complete the lab, clickthe Generate button. This should ensure that the path to your ip is set
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