1February 18, 2009 http://csg.csail.mit.edu/6.375 L07-1Modeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 18, 2009L07-2http://csg.csail.mit.edu/6.375The PlanNon-pipelined processor⇐Two-stage synchronous pipelineTwo-stage asynchronous pipelineSome understanding of simple processor pipelines is needed to follow this lecture2February 18, 2009L07-3http://csg.csail.mit.edu/6.375Instruction settypedef enum {R0;R1;R2;…;R31} RName;An instruction set can be implemented using many different microarchitecturestypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName value; RName addr;} Store} Instr deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 18, 2009L07-4http://csg.csail.mit.edu/6.375Tagged Unions: Bit Representation00 dst src1 src201 cond addr10 dst addr11 dst immtypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);Automatically derived representation; can be customized by the user written pack and unpack functions3February 18, 2009L07-5http://csg.csail.mit.edu/6.375Non-pipelined Processorfetch & execute pciMem dMemrfCPUmodule mkCPU#(Mem iMem, Mem dMem)();Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1;rule fetch_Execute ...endmoduleFebruary 18, 2009L07-6http://csg.csail.mit.edu/6.375Non-pipelined processor rulerule fetch_Execute (True);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: beginrf.upd(rd, rf[ra]+rf[rb]);pc <= predIaendtagged Bz {cond:.rc,addr:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; endtagged Load {dest:.rd,addr:.ra}: beginrf.upd(rd, dMem.read(rf[ra]));pc <= predIa;endtagged Store {value:.rv,addr:.ra}: begindMem.write(rf[ra],rf[rv]);pc <= predIa;endendcaseendrulemy syntaxrf[r] ≡ rf.sub(r)Assume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cycle4February 18, 2009L07-7http://csg.csail.mit.edu/6.375The PlanNon-pipelined processorTwo-stage synchronous pipeline ⇐Two-stage asynchronous pipelineFebruary 18, 2009L07-8http://csg.csail.mit.edu/6.375Two-stage SynchronousPipelinefetch & decodeexecutebuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5Actions to be performed in parallel every cycle: Fetch Action: Decodes the instruction at the current pc and fetches operands from the register file and stores the result in buReg Execute Action: Performs the action specified in buReg and updates the processor state (pc, rf, dMem)pc rf dMem5February 18, 2009L07-9http://csg.csail.mit.edu/6.375Instructions & Templatestypedef union tagged { struct {RName dst; Value op1; Value op2} EAdd;struct {Value cond; Iaddress tAddr} EBz;struct {RName dst; Daddress addr} ELoad;struct {Value data; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);typedef union tagged {struct {RName dst; RName src1; RName src2} Add;struct {RName cond; RName addr} Bz;struct {RName dst; RName addr} Load;struct {RName value; RName addr} Store;} Instr deriving(Bits, Eq);buReg contains instruction templates, i.e., decoded instructionsFebruary 18, 2009L07-10http://csg.csail.mit.edu/6.375Fetch & Decode ActionFills the buReg with a decoded instructionfunction InstrTemplate newIt(Instr instr);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}:return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]};tagged Bz {cond:.rc,addr:.addr}:return EBz{cond:rf[rc],addr:rf[addr]};tagged Load {dst:.rd,addr:.addr}:return ELoad{dst:rd,addr:rf[addr]};tagged Store{value:.v,addr:.addr}:return EStore{value:rf[v],addr:rf[addr]};endcaseendfunctionbuReg <= newIt(instr); no extra gates!6February 18, 2009L07-11http://csg.csail.mit.edu/6.375Execute Action: Reads buRegand modifies state (rf,dMem,pc)case (buReg) matches tagged EAdd{dst:.rd,src1:.va,src2:.vb}: begin rf.upd(rd, va+vb); pc <= predIa; end tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); pc <= predIa; endtagged EStore{value:.vv,addr:.av}: begin dMem.write(av, vv); pc <= predIa; endtagged EBz {cond:.cv,addr:.av}:if (cv != 0) then pc <= predIa;else begin pc <= av; endendcaseFebruary 18, 2009L07-12http://csg.csail.mit.edu/6.375Issues with buRegfetch & decodeexecutebuRegbuReg may not always contain an instruction. Why?Can’t update buReg in two concurrent actionsfetchAction; executeActionpc rf dMem7February 18, 2009L07-13http://csg.csail.mit.edu/6.375fetch & decodeexecutepcrfCPUbuRegSynchronousPipelinefirst attemptrule SyncTwoStage (True);let instr = iMem.read(pc); let predIa = pc+1;Action fetchAction = actionbuReg <= Valid newIt(instr);pc <= predIa;endaction;case (buReg) matches …calls fetchAction or puts Invalid in buReg…endcaseendcase endruleFebruary 18, 2009L07-14http://csg.csail.mit.edu/6.375Executecase (buReg) matches tagged Valid .it: case (it) matchestagged EAdd{dst:.rd,src1:.va,src2:.vb}: beginrf.upd(rd, va+vb); fetchAction; end tagged ELoad{dst:.rd,addr:.av}: beginrf.upd(rd, dMem.read(av)); fetchAction; endtagged EStore{value:.vv,addr:.av}: begindMem.write(av, vv); fetchAction; endtagged EBz {cond:.cv,addr:.av}:if (cv != 0) then fetchAction;else begin pc <= av; buReg <= Invalid; endendcasetagged Invalid: fetchAction;endcasefetch & decodeexecutepcrfCPUbuReg8February 18, 2009L07-15http://csg.csail.mit.edu/6.375Pipeline Hazardsfetch & decodeexecutebuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5I1Add(R1,R2,R3)I2Add(R4,R1,R2)pc rf dMemFebruary 18, 2009L07-16http://csg.csail.mit.edu/6.375SynchronousPipelinecorrectedrule SyncTwoStage (True);let instr = iMem.read(pc); let predIa = pc+1;Action fetchAction = actionif stallFunc(instr, buReg) then buReg <=Invalidelse beginbuReg <= Valid newIt(instr);pc <= predIa; endendaction;case (buReg) matches … no change …endcaseendcase endrulefetch & decodeexecutepcrfCPUbuRegHow do we detect stalls?9February 18, 2009L07-17http://csg.csail.mit.edu/6.375The Stall Functionfunction Bool stallFunc (Instr instr, Maybe#(InstTemplate) mit);
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