1Modeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologygyFebruary 23, 2011 L07-1http://csg.csail.mit.edu/6.375Instruction settypedef enum {R0;R1;R2;…;R31} RName;typedef union tagged{struct {RName dst; RName src1; RName src2;} Add;struct {RName condR; RName addrR;} Bz;struct {RName dst; RName addrR;} Load;struct {RName valueR; RName addrR;} Store} Instr deriving(Bits, Eq);An instruction set can be implemented using many different microarchitecturestypedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 23, 2011L07-2http://csg.csail.mit.edu/6.3752Deriving Bitstypedef struct { … } Fooderiving (Bits);To store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack)Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit deriving (Bits);type (simple concatenation of bit representations of components)It is possible to customize the pack/unpack operations to any specific desired representationFebruary 23, 2011L07-3http://csg.csail.mit.edu/6.375Tagged Unions: Bit Representationtypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct{RName condR; RName addrR;} Bz;00 dst src1 src201 condR addrRstruct{RName condR; RName addrR;} Bz;struct {RName dst; RName addrR;} Load;struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);10 dst addrR11 dst immAutomatically derived representation; can be customized by the user written pack and unpack functionsFebruary 23, 2011L07-4http://csg.csail.mit.edu/6.3753The PlanNon-pipelined processorNonpipelined processorTwo-stage Inelastic pipelineTwo-stage Elastic pipeline –next Two-stage Elastic pipeline –next lectureSome understanding of simple processor pipelines is needed to follow this lectureFebruary 23, 2011L07-5http://csg.csail.mit.edu/6.375Non-pipelined ProcessorpcrfCPUfetch & execute iMem dMemmodule mkCPU#(Mem iMem, Mem dMem)();Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1;rule fetch_Execute ...endmoduleFebruary 23, 2011L07-6http://csg.csail.mit.edu/6.3754Non-pipelined processor rulerule fetch_Execute (True);case (instr) matchestaggedAdd {dst:.rd,src1:.ra,src2:.rb}: beginPattern matchingrf.upd(rd, rf[ra]+rf[rb]);pc <= predIaendtagged Bz {condR:.rc,addrR:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; endtagged Load {dest:.rd,addrR:.ra}: beginrf.upd(rd, dMem.read(rf[ra]));pc <= predIa;my syntaxrf[r] rf.sub(r)endtagged Store {valueR:.rv,addrR:.ra}: begindMem.write(rf[ra],rf[rv]);pc <= predIa;endendcaseendruleAssume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cycleFebruary 23, 2011L07-7http://csg.csail.mit.edu/6.375Register FileHow many read ports?How many write ports?Concurrency properties?February 23, 2011L07-8http://csg.csail.mit.edu/6.3755The PlanNon-pipelined processorNonpipelined processorTwo-stage Inelastic pipeline Two-stage Elastic pipelineTwo-stage Elastic pipelineFebruary 23, 2011L07-9http://csg.csail.mit.edu/6.375Two-stage InelasticPipelinefetch & decodeexecutebuRegpc rf dMembuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5Actions to be performed in parallel every cycle:Fetch Action: Decodes the instruction at the current pc Fetch Action: Decodes the instruction at the current pc and fetches operands from the register file and stores the result in buReg Execute Action: Performs the action specified in buReg and updates the processor state (pc, rf, dMem)rule InelasticPipeline2(True);fetchAction; executeAction; endruleFebruary 23, 2011L07-10http://csg.csail.mit.edu/6.3756Instructions & TemplatesbuReg contains instruction templates, i.e., decoded instructionstypedef union taggedtypedef union tagged {struct {RName dst; RName src1; RName src2} Add;struct {RName condR; RName addrR} Bz;struct {RName dst; RName addrR} Load;struct {RName valueR; RName addrR} Store;} Instr deriving(Bits, Eq);typedef union tagged { struct {RName dst; Value op1; Value op2} EAdd;struct {Value cond; Iaddress tAddr} EBz;struct {RName dst; Daddress addr} ELoad;struct {Value val; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);February 23, 2011L07-11http://csg.csail.mit.edu/6.375Fetch & Decode ActionFills the buReg with a decoded instructionbuReg <= newIt(instr); function InstrTemplate newIt(Instr instr);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}:return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]};tagged Bz {condR:.rc,addrR:.addr}:return EBz{cond:rf[rc],tAddr:rf[addr]};taggedLoad {dst:.rd,addrR:.addr}:taggedLoad {dst:.rd,addrR:.addr}:return ELoad{dst:rd,addrR:rf[addr]};tagged Store{valueR:.v,addrR:.addr}:return EStore{val:rf[v],addr:rf[addr]};endcase endfunction February 23, 2011L07-12http://csg.csail.mit.edu/6.3757Execute Action: Reads buRegand modifies state (rf,dMem,pc)case (buReg) matches tagged EAdd{dst:.rd,op1:.va,op2:.vb}: bif d(d +b)begin rf.upd(rd, va+vb); pc <= predIa; end tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); pc <= predIa; endtagged EStore{val:.vv,addr:.av}: begin dMem.write(av, vv); pc <= predIa; endtagged EBz {cond:.cv,tAddr:.av}:if (cv != 0) then pc <= predIa;else begin pc <= av; Invalidate buRegendendcaseWhat does this mean?February 23, 2011L07-13http://csg.csail.mit.edu/6.375Issues with buRegfetch & decodeexecutebuRegpc rf dMembuRegbuReg may not always contain an instruction. Why? start cycle Execute stage may kill the fetched instructions because of branch mispredictionMaybe type to the rescue …Can’t update buReg in two concurrent actionsfetchAction; executeActionFold them togetherFebruary 23, 2011L07-14http://csg.csail.mit.edu/6.3758InelasticPipelinefirst attemptfetch & decodeexecutepcrfCPUbuRegrule SyncTwoStage (True);letinstr=iMem read(pc);letinstr= iMem.read(pc); let predIa = pc+1;Action fetchAction = actionbuReg <= Valid newIt(instr);pc <= predIa;endaction;case (buReg) matches each instruction execution calls fetchActionor puts Invalid in buReg …endcaseendcase endruleFebruary 23, 2011L07-15http://csg.csail.mit.edu/6.375Executecase (buReg) matches
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