Verilog 1 - Fundamentals6.375 Course Structure First half of term before spring break6.375 Course Structure Second half of term after spring break6.375 Course Structure Semester long design projectSlide 56.375 Course Structure Grade breakdown6.375 Course Structure Opportunities for exceptional projectsVerilog FundamentalsOriginally designers used manual translation + bread boards for verificationHardware design languages enabled logic level simulation and verificationDesigners began to use HDLs for higher level verification and design explorationHDL behavioral models act as a precise and executable specificationOnce designs were written in HDLs tools could be used for automatic translationSlide 14Guarded atomic actions can help us to efficiently raise the abstraction levelVarious hardware design languages are availableSlide 17Primary Verilog data type is a bit-vector where bits can take on one of four valuesThe Verilog keyword wire is used to denote a standard hardware netVerilog includes ways to specify bit literals in various basesVerilog BasicsA Verilog module includes a module name and a port listSlide 23A module can instantiate other modules creating a module hierarchySlide 25Slide 26Verilog supports connecting ports by position and by nameLet’s review how to turn our schematic diagram into structural VerilogSlide 29Slide 30Functional Verilog can roughly be divided into three abstraction levelsGate-level Verilog uses structural Verilog to connect primitive gatesContinuous assignment statements assign one net to another or to a literalUsing continuous assignments to implement an RTL four input multiplexerVerilog RTL includes many operators in addition to basic boolean logicVerilog RTL operatorsAlways blocks have parallel inter-block and sequential intra-block semanticsSlide 38Slide 39Slide 40Slide 41Continuous and procedural assignment statements are very differentAlways blocks can contain more advanced control constructsWhat happens if the case statement is not complete?Slide 45So is this how we make latches and flip-flops?To understand why we need to know more about Verilog execution semanticsSlide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Non-blocking procedural assignments add an extra event queueSlide 57Slide 58Common patterns for latch and flip-flop inferenceSix guidelines for using blocking and non-blocking assignment statmentsBehavioral Verilog is used to model the abstract function of a hardware moduleVerilog can be used to model the high-level behavior of a hardware blockDelay statements should only be used in test harnessesEven synthesizable blocks can be more behavioral in natureSystem tasks are used for test harnesses and simulation managementWhich abstraction is the right one?Take away pointsVerilog 1 - Fundamentals6.375 Complex Digital SystemsChristopher BattenFebruary 9, 2006FAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 26.375 Course StructureFirst half of term before spring break•Lectures MWF, 2:30pm to 4:00pm in 32-124•Four lab assignments–Lab #1 : Verilog RTL for 2-stage SMIPSv2 processor–Lab #2 : Push SMIPSv2 processor through to layout–Lab #3 : Bluespec RTL for 4-stage SMIPSv2 processor–Lab #4 : Bluespec RTL for non-blocking cache•Project preparation–Form project team (2-3 students)–Prepare preliminary project proposal•Closed-book 90 minute quiz (March 24)6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 36.375 Course StructureSecond half of term after spring break•Weekly project meetings with instructors•Weekly milestones with 1-2 page report•Final project presentations last week of classes•Final project report –Approximately 15-20 pages–Due May 17 (no extensions!)6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 46.375 Course StructureSemester long design project•Two standard projects with fixed interfaces, infrastructure, and testbenches–SMIPS microprocessor•High performance (e.g. multicore, ooo superscalar)•Low power (e.g. fetch throttling, instruction fusion)•Minimal area (e.g. multiplexed byte-wide datapath)–SMIPS memory system•Cache-coherent multicore•DRAM memory access scheduler•Hardware prefetching6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 56.375 Course StructureSemester long design project•Custom or non-standard projects–Submit 2 page proposal by March 17 for approval–C/C++/Java reference implementation by March 22–Ex: MP3 player, graphics pipeline, network processor802.11a Encoder, 20056.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 66.375 Course StructureGrade breakdownFour labs 30%Quiz 20%Project milestones 25%Final project report 25%6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 76.375 Course StructureOpportunities for exceptional projects•Possibility of fabrication–Implement in 180nm technology–Summer and fall commitment–Significant work is required to prepare final project for fabrication•Possibility of targeting FPGA–Various development boards are available–Requires different toolchain6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 8Verilog Fundamentals•History of hardware design languages•Data types•Structural Verilog•Functional Verilog–Gate level–Register transfer level–High-level behavioralFAFA FA FAmodule adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 9Originally designers used manual translation + bread boards for verificationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsBreadBoardNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 10Hardware design languages enabled logic level simulation and verificationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 11Designers began to use HDLs for higher level verification and design
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