Physical Effects: Delay6.375 Standard Cell Design FlowMeasuring Chip “Quality”Iron Law of PerformanceBasic CMOS ComponentsMetal Oxide-Semiconductor Field-Effect (MOSFET) TransistorKey qualitative characteristics of MOSFET transistors affecting delayCMOS Transistors, Gates, and WiresThe most basic CMOS gate is an inverterSlide 10A simple RC model for the inverter can provide significant insightSlide 12Slide 13Slide 14Larger gates are faster since they decrease Reff (but they also increase Cd!)More complicated gates use more transistors in pullup/pulldown networksSeries and parallel MOSFET networks provide natural duals of each otherNAND and NOR gates illustrate the dual nature of the pullup/pulldown networksA methodical approach to build more complex gatesExample of complex gateExamples illustrating unit-less delay (d) of gates with equal drive strength (Reff)Examples illustrating unit-less delay (d) of gates with similar areaWhich gate topology and transistor sizing is optimal?Optimal sizing and delays for example topologiesSlide 25Wires are an old problemModern interconnect stacks have six to nine or more metal layersWire resistance is a function of height, width, and lengthWire capacitance is relative to the substrate and to neighboring wiresSlide 30This IBM experimental 130nm process includes two metals and two dielectricsDistributed RC wire model gives accurate results but is computationally expensiveLumped model can provide a quick reasonable approximationEstimate the rise time of node A using an RC delay modelSlide 35How many stages of inverters required if want to drive large load?A good rule-of-thumb is to target a stage effort around fourLarge RC makes long wires slowAdding repeaters gives linear growth in delaySeveral issues with repeater insertionWire delay in standard-cell flowWire Delay: Impact on RTLIn deep submicron technologies many predicted an interconnect doomsdayIs there really an interconnect doomsday looming?Slide 45No doomsday, just one more physical design issue to carefully managePhysical Effects: Delay6.375 Complex Digital SystemsKrste AsanovicMarch 5, 2007CdRPCgCW/2CW/2RW6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 2Bluespec SystemVerilog sourceVerilog 95 RTLVerilog simVCD outputDebussyVisualizationBluespec CompilerfilesBluespec tools3rd party toolsLegendRTL synthesisgatesCBluespec C simCycleAccurateBlueviewHow do RTL choices affect resulting physical design?6.375 Standard Cell Design Flow6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 3Measuring Chip “Quality”Most important metrics for a chip design:•Area–Size affects manufacturing and packaging costs•Performance–Does chip meet market performance goals?•Power–Peak power affects packaging cost (current supply, heat removal)–Energy usage affects battery life6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 4Iron Law of Performance € Performance=OperationsClock Cycle×Clock CyclesSecondConcurrency in RTL DesignClock Frequency of Physical DesignThese are not independent parameters!Clock frequency set by delay of circuit components in critical path6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 5Basic CMOS Componentsinput0input1outputTransistorsWiresGates6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 6Metal Oxide-Semiconductor Field-Effect (MOSFET) TransistorCONDUCTION:If a channel exists, a horizontal field will cause a drift current from the drain to the source.EhSource diffusionDrain diffusionGatebulkINVERSION:A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain.EvInversionhappens here6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 7Key qualitative characteristics of MOSFET transistors affecting delay•Increase Width (W) Increase current Decrease Reff•Increase Length (L) Decrease current Increase Reff•Cgate proportional to (W x L) and Cdrain proportional to WWidthLengthCgateCdrainReffVoutVin6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 8CMOS Transistors, Gates, and Wiresinput0input1outputTransistorsWiresGates6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 9The most basic CMOS gate is an inverterVinVoutWN/LNWP/LPLet’s make the following assumptions1. All transistors are minimum length2. All gates should have equal rise/fall times. Since PMOS are ~twice as slow as NMOS they must be twice as wide to have the same effective resistance3. Normalize all transistor widths to minimum width NMOS2α1α6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 10The most basic CMOS gate is an inverterVinVoutWN/LNWP/LP2α1αA YVDDGNDPMOSNMOS6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 11A simple RC model for the inverter can provide significant insightReff = Reff,N = Reff,P Cg= Cg,N + Cg,P Cd= Cd,N + Cd,PVinVoutVinCgCdReffReffVout6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 12A simple RC model for the inverter can provide significant insightVinCgCdReffReffVoutCL6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 13A simple RC model for the inverter can provide significant insightCgCdReffReffVoutCLVin = “0” Charge RC Time Constant (TPLH) = Reff x ( Cd + CL )6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 14The most basic CMOS gate is an inverterCgCdReffReffVoutCLVin = “1” Discharge RC Time Constant (TPHL) = Reff x ( Cd + CL )6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 15Larger gates are faster since they decrease Reff (but they also increase Cd!)21 Cd = (0.5x1.42) + (1x2.40) = 3.11 fF CL = (0.5x1.55) + (1x1.48) = 2.26 fFCd+CL = 5.37 fF TPLH = 2.2 x (10.83/1) x 5.37 = 128ps TPHL = 2.2 x (4.93/0.5) x 5.37 = 116ps214221 Cd = (1x1.42) + (2x2.40) = 3.66 fF CL = (0.5x1.55) + (1x1.48) = 2.26 fFCd+CL = 5.92 fF TPLH = 2.2 x (10.83/2) x 5.92 = 70.5ps TPHL = 2.2 x (4.93/1) x 5.92 = 64.2psIgnores the fact that previous gate now must drive a bigger gate capacitance!Param Value UnitsCd,N/μm1.42 fF/μmCd,P/μm2.40 fF/μmCg,N/μm1.55 fF/μmCg,P/μm1.48 fF/μmReff,N x μm4.93 kΩ/μmReff,P x μm10.83 kΩ/μmProcess gen = 0.25μmSupply voltage = 5VMin width NMOS = 0.5μmDouble size of driver6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 16More complicated gates use more transistors in pullup/pulldown
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