1BSV1f ESL2DiBSV1for ESL2DesignRishiyur S. Nikhil, PhD.CTO, Bluespec, Inc.© Bluespec, Inc., 2008Lecture in 6.375, MITMarch 10, 20081: Bluespec SystemVerilog2: Electronic System LevelSoCs: complex assemblies of many application—specific blocks (IPs)On-chip memory banksApplication-specific processing unitsGeneral-purpose processorsprocessing units2Structured on-chip networksMany IPs must be implemented in HW to save power.And, at many power/performance operating points2Central SoC design concernsEarlysoftwareSW development needs platforms earlySW development needs fast platformsSoftwareHW/SW interface (e.g., mem-mapped register read/write)avail. early,fast sim,but notaccurateFirst HW models3CorrectnessHW ImplementationHW-accurate,but avail. late,slow sim Central SoC design concerns (contd.): reuse models, implementations, testbenchesAcross chips and in derivative chipsSoC 1 SoC 2 SoC nDuring refinementand exploration43The only feasible approachRapid prototyping for wireless designs: the five-ones approach, M.Rupp, A.Burg and fiveones approach, M.Rupp, A.Burg and E.Beck, Signal Processing 83:7, 2003, pp. 1427-1444 “One code, one environment, one team, one documentation, one revision control”I.e., need a single, consistent language and 5I.e., need a single, consistent language and environment for the whole ESL design process But even this is not enoughBSV addresses SoC design concernsEarlysoftwareSoftwareHW/SW interface (e.g., mem-mapped register read/write)First HW models6HW Implementation• One language/ semantics• Atomicity: correctness• Strong parameterization, higher-order descriptions: reuse• Atomicity: composability, control-adaptive reuse• Synthesizability even for early models (faster sim, FPGA accel)• C, SystemC integration4BSV enables a top-down refinement methodologyHighlevelDesign IPVerification IPSoftwareHi hllToolsHigh-levelTransactionalI/FHigh-levelTransactionalI/FvoidTestBench::Result( void* tbPointer){TestBench* tb = reinterpret _cast< TestBench* >( tbPointer );unsigned data[4];doResp( tb->drv0, &(tb->out[0]), data );Add FunctionalityAdd Ahit t lInitialTestbench(approx)ExploreArchitecturesInitial IP(approx)AddFunctionalityAddFunctionalityRefine/ReplaceFPGA/Emulation(>>100X speed)Bluesim(10X speed)RTL simulation(1X speed)BluespecSynthesisororExecution at every stepVerify/Analyze/Verilog7High-levelTransactionalI/FFinal Bus/InterconnectI/FvoidTestBench::Result( void* tbPointer){TestBench* tb = r einterpret_cast < TestBench* >( tbPoint er );unsigned data[4];doResp( tb->drv0, &(tb->out[0]), data );cout << "data is: " << hex << data[0] << data[1] << data[2] << data[3] << endl;Tcl_Obj* cmd = Tcl_NewStringObj( " reportResults ", -1 );for( int i=0; i< 4; i++ )voidTestBench::Result( void* tbPointer){TestBench* tb = r einterpret_cast < TestBench* >( tbPoint er );unsigned data[4];doResp( tb->drv0, &(tb->out[0]), data );cout << "data is: " << hex << data[0] << data[1] << data[2] << data[3] << endl;Tcl_Obj* cmd = Tcl_NewStringObj( " reportResults ", -1 );for( int i=0; i< 4; i++ )voidTestBench::Result( void* tbPointer){TestBench* tb = reinterpret _cast< TestBench* >( tbPointer );unsigned data[4];doResp( tb->drv0, &(tb->out[0]), data );cout << "data is: " << hex << data[0] << data[1] << data[2] << data[3] << endl;Tcl_Obj* cmd = Tcl_NewStringObj( " reportResults ", -1 );for( int i=0; i< 4; i++ )Architectural DetailFinalTestbenchFinal IPRTLsynthesisPowerEstimationyDebugTopics todayEarly models: executable, synthesizableFSMFSMsInterface abstractionParameterizable microarchitecturesC/SystemC integration85Early models(executable, synthesizable)9Rules allow early models to be like executable and synthesizable specs: e.g., an ISS (instruction set simulator)BSV code:• Close to spec• No extraneous logic for managing shared resources• Scalable – incrementally add functionalityExcerpt from Assembler Manualrule add(instruction_D.first.op == Add && cpuState == Execute);Instruction add = instruction_D.first;// Get the register values involvedlet a = regfile.sub(add.ra);let b = regfile.sub(add.rb);// Perform the additionlet d = add32(a, b);// Writeback the resultsupdateregfile(add.rd, d);y10update_eg e(add d, d);// Calculate the overflow bitBool overflow = (((a[31] == 1) && (b[31] == 1) &&(d[31] == 0)) || ((a[31] == 0) && (b[31] == 0) &&(d[31] == 1)));// Update Flagsupdate_condition0_ovl(add.rc, d, overflow);update_carry_overflow(add.oe, overflow, False, 1'b0);increment_pc;endrule6FPGA accelerationSince all of BSV is synthesizable, even such early, functional models can be synthesized early, functional models can be synthesized into RTL and run on FPGA platforms/emulators Not optimized, but still faster than simulationTypical uses: Architectural explorationFast emulation for earlier verification11Fast emulation for earlier verification Early software developmentFSMs127The StmtFSM packageBSV’s rules are of course powerful enough to express any FSMenough to express any FSM. A rule’s condition identifies a state A rule’s Action specifies the state transition and any other actions for that stateHowever there are some common 13However, there are some common idioms (“design patterns”) for FSMs which are made simpler with syntactic supportExampleInitialize a memory with a 2-D pattern An FSM is needed since the memory can only accept 1 write per cyclerule prelude (p == Pre);typedef enum { Pre Loop Post Done} Phasesrule prelude (p == Pre);... pre initialization actions ...p <= Loop; i <= 0; j <= 0; addr <= addr0;endrulerule loop (p == Loop && (i < nI) && (j < nJ));mem.write (addr, f (i, j));addr <= addr + 1;if (j < nJ-1)j <= j + 1;else beginj <= 0;f(i,j)nJnIijaddr014typedef enum { Pre, Loop, Post, Done} Phasesderiving (Bits, Eq);Reg#(Phases) p <- mkReg (Pre);Reg#(int) i <- mkRegU;Reg#(int) j <- mkRegU;Reg#(Addr) addr <- mkRegU;jif (i < nI-1)i <= i + 1;elsep <= Post;endendrulerule postlude (p == Post);... post-initialization actions ...p <= Done;endrule8ExampleInitialize a memory with a 2-D pattern (must be written as an FSM since only memory can only accept 1 write per cycle)Stmt s = seqaction... pre initialization actions ...addr <= addr0;endactionfor (i <= 0; i < nI; i <= i + 1)for (j <= 0; j < nJ; j <= j + 1) actionmem.write (addr, f (i, j));addr <= addr + 1;endaction;...post-initialization actions...import StmtFSM *f(i,j)nJnIijaddr015... postinitialization actions...endseq;FSM fsm <= mkFSM
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