RTL-to-Gates Synthesis using Synopsys Design Compiler6.375 Tutorial 4March 2, 2008In this tutorial you will gain experience using Synopsys Design Compiler (DC) to perform hardwaresynthesis. A synthesis tool takes an RTL hardware description and a standard cell library asinput and produces a gate-level netlist as output. The resulting gate-level netlist is a completelystructural description with only standard cells at the leaves of the design. Internally, a synthesis toolperforms many steps including high-level RTL optimizations, RTL to unoptimized boolean logic,technology independent optimizations, and finally technology mapping to the available standardcells. A synthesis tool is only as good as the standard cells which it has at its disposal. GoodRTL designers will familiarize themselves with the target standard cell library so that they candevelop a solid intuition on how their RTL will be synthesized into gates. In this tutorial we willuse Synopsys Design Compiler to elaborate RTL, set optimization constraints, synthesize to gates,and prepare various area and timing reports.Synopsys provides a libr ary called Design Ware which includes highly optimized RTL for arithmeticbuilding blocks. For example, the Design Ware libraries contain adders, multipliers, comparators,and shifters. DC can automatically determine when to use Design Ware components and it canthen efficiently synthesize these components into gate-level implementations. In this tutorial wewill learn more about what Design Ware components are available and how to best encourage DCto use them.It is important to carefully monitor the synthesis tool to identify issues which might negativelyimpact the area, power, or performance of the design. We will learn how to read the various DCtext reports and h ow to use the graphical Synops y s Design Vision tool to visualize the synthesizeddesign.The following documentation is located in the course locker (/mit/6.375/doc) and provides addi-tional information about Design Compiler, Design Vision, the Design Ware libraries, and the Tower0.18 µm Standard Cell Library.• tsl-180nm-sc-databook.pdf - Databo ok for Tower 0.18 µm Standard Cell Library• presto-HDL-compiler.pdf - Guide for the Verilog Complier used by DC• dc-user-guide.pdf - Design Compiler user guide• dc-quickref.pdf - Design Compiler quick reference• dc-constraints.pdf - Design Compiler constraints and timing reference• dc-opt-timing-analysis.pdf - Design Compiler optimization and timing analysis ref• dc-shell-basics.pdf - Basics of using the DC shell• dc-tcl-user-guide.pdf - Basics of writing TCL scripts for Design Compiler• design-ware-quickref.pdf - Design Ware quick reference• design-ware-user-guide.pdf - Design Ware user guide• design-ware-datasheets - Directory containing datasheets on each DW component• dv-tutorial.pdf - Design Vision Tutorial• dv-user-guide.pdf - Design Vision User Guide6.375 Tutorial 4, Spring 2008 2Getting startedBefore using the 6.375 toolflow you must add the course locker and run the course s etup script withthe following two commands.% add 6.375% source /mit/6.375/setup.cshFor this tutorial we will be using an unpipelined SMIPSv1 processor as our example RTL d esign.You s hould create a working directory and checkout the SMIPSv1 example project from the courseCVS repository using the following commands.% mkdir tut4% cd tut4% cvs checkout examples/smipsv1-1stage-v% cd examples/smipsv1-1stage-vBefore starting, take a look at the subdirectories in the smips1-1stage-v project directory. Figure 1shows the sys tem diagram which is implemented by the example code. When pushing designsthrough the physical toolflow we will often refer to the core. The core module contains everythingwhich will be on-chip, wh ile blocks outside the core are assume to be off-chip. For this tutorialwe are assuming that the processor and a combinational memory are located within the core. Acombinational memory means that the read address is specified at the beginning of the cycle, andthe read data returns during the same cycle. Building large combin ational memories is relativelyinefficient. It is much more common to use synchronous memories. A synchronous memory meansthat the read address is specified at the end of a cycle, and the read data returns during thenext cycle. From Figure 1 it should be clear that the unpipelined SMIPSv1 pr ocessor requirescombinational memories (or else it would turn into a f ou r stage pipeline). For this tutorial we willnot be using a real combinational memory, but instead we will use a dummy memory to emulaterd0rd1RegFile>> 2SignExtendir[15:0]RegFileDataMemvalrwCmpeq?Instruction Memvalpc+4branch+4DecoderControlSignalstohosttohost_entestrig_tohostir[25:21]ir[20:16]Addwdataaddrrdatarf_wenwb_selir[20:16]PCpc_selFigure 1: Block diagram for Unpipelined SMIPSv1 Processor6.375 Tutorial 4, Spring 2008 3the combinational delay throu gh the memory. Examine the source code in src and comparesmipsCorertl with smipsCore synth. The smipsCore rtl module is used for simulating theRTL of the SMIPSv1 processor an d it includes a functional model f or a large on-chip combinationalmemory. The smipsCore synth module is used for synthesizing the SMIPSv1 processor and it usesa dummy memory. The dummy m emory combinationally connects the memory request bus tothe memory response bus with a series of standard-cell buffers. Obviously, this is not fun ctionallycorrect, but it will help us illustrate more reasonable critical paths in the design. In later tutorials,we will start us ing memory generators which will create synchronous on-chip SRAMs.Now examine the build directory. This directory will contain all generated content includingsimulators, synthesized gate-level Verilog, and final layout. In this course we will always try to keepgenerated content separate from our source RTL. This keeps our project directories well organized,and helps prevent us f rom unintentionally modifying our source RTL. There are subdirectories inthe build d ir ectory for each major step in the 6.375 toolflow. These subdir ectories contain scriptsand configuration files for runn ing the tools required for that step in the toolflow. For this tutorialwe will work exclusively in the dc-synth directory.Synthesizing the ProcessorWe will begin by running several DC commands manually before learning how we can automate thetool with scripts. DC can generate a large number of output files, so we will be running DC
View Full Document
Unlocking...