Verilog 2 - Design ExamplesCourse administrative notesVerilog Design ExamplesStatic elaboration enables generation of hardware at synthesis timeParameters are bound during static elaboration creating flexible modulesSlide 6Generate blocks can execute loops and conditionals during static elaborationCombining parameters + generate blocks enables more powerful elaborationGenerate statements are useful for more than just module instantiationTraditionally designers have resorted to behavioral inference for elaborationSlide 11Behavioral GCD model is written within a single always block with C like structureSimple test harness for behavioral model of GCDSlide 14The first step is to carefully design an appropriate port interfaceNext develop a datapath which has the proper functional unitsNext develop a datapath which has the proper functional unitsSlide 18Finally add the control unit to sequence the datapathDatapath module interfaceTry to contain all functionality in leaf modulesSlide 22Control unit requires a simple state machine for valid/ready signalsImplementing the control logic finite state machine in VerilogImplementing the control signal outputs for the finite state machineImplementing the state transitions for the finite state machineRTL test harness requires properly handling the ready/valid signalsWe can compare the behavioral and RTL implementations to verify correctnessSlide 29SMIPS is a simple MIPS ISA which includes three variantsSMIPSv1 ISAThe first step is to carefully design an appropriate port interfaceSMIPSv1 Block Diagram How do we start implementing?Why memories, datapath, and control? To exploit the structure inherent in eachStanford MIPS-X 5 Stage, 20MHz RISC ProcessorBerkeley T0 8 Lane Vector MicroprocessorStanford Imagine Streaming Application EngineMIT RAW 16 Tiled General Purpose ProcessorPure cell-based ASIC flows can no longer ignore the importance of partitioningLet’s identify the memories, datapaths, and random logic in our SMIPSv1 designSlide 41SMIPSv1 datapath interface contains controls signals and memory data busesRegister file with two combinational read ports and one write portVerilog for SMIPSv1 control logicSlide 45Take away pointsVerilog 2 - Design Examples6.375 Complex Digital SystemsChristopher BattenFebruary 13, 20066.375 Spring 2006 • L03 Verilog 2 - Design Examples • 2Course administrative notes•If you did not receive an email over the weekend concerning the course then you are not on the student mailing list - please email 6.375-staff•Lab 1 has been posted on the course website. It is due Friday, February 24–2-stage SMIPSv2 processor RTL checked into CVS–Critical thinking questions•Tutorials on VCS, CVS, and SMIPS assembly programming will be posted this week6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 3Verilog Design Examples•Parameterized Static Elaboration•Greatest Common Divisor•Unpipelined SMIPSv1 processor6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 4Static elaboration enables generation of hardware at synthesis timeRegisterTransfer LevelGate LevelAuto Place + RouteTestResultsSimulateElaboratedDesignLogic SynthesisStatic ElaborationTestResultsSimulateWe will look at two forms of static elaboration: (1) parameters and (2) generate blocks6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 5Parameters are bound during static elaboration creating flexible modulesmodule vcMux2#( parameter WIDTH = 1 )( input [WIDTH-1:0] in0, in1, input [1:0] sel, output [WIDTH-1:0] out ); always @(*) begin case ( sel ) 1’d0 : out = in0; 1’d1 : out = in1; default : out = {WIDTH{1’bx}}; endcase endendmoduleInstantiation SyntaxvcMux2#(32) alu_mux( .in0 (op1), .in1 (bypass), .sel (alu_mux_sel), .out (alu_mux_out) );6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 6Parameters are bound during static elaboration creating flexible modulesmodule vcERDFF_pf#( parameter WIDTH = 1, parameter RESET_VALUE = 0 )( input clk, input reset, input [WIDTH-1:0] d, input en, output reg [WIDTH-1:0] q ); always @( posedge clk ) if ( reset ) q <= RESET_VALUE; else if ( en ) q <= d;endmoduleInstantiation SyntaxvcERDFF_pf#(32,32’h10) pc_pf( .clk (clk), .reset (reset), .en (pc_enable), .d (pc_mux_out), .q (pc));6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 7Generate blocks can execute loops and conditionals during static elaborationmodule adder ( input [3:0] op1,op2, output cout, output [3:0] sum ); wire [4:0] carry; assign carry[0] = 1’b0; assign cout = carry[4] genvar i; generate for ( i = 0; i < 4; i = i+1 ) begin : ripple FA fa( op1[i], op2[i], carry[i], carry[i+1] ); end endgenerateendmodule All genvars must be disappear after static elaborationGenerated names will have ripple[i]. prefix6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 8Combining parameters + generate blocks enables more powerful elaborationmodule adder#( parameter WIDTH = 1 )( input [WIDTH-1:0] op1,op2, output cout, output [WIDTH-1:0] sum ); wire [WIDTH:0] carry; assign carry[0] = 1’b0; assign cout = carry[WIDTH]; genvar i; generate for ( i = 0; i < WIDTH; i = i+1 ) begin : ripple FA fa( op1[i], op2[i], carry[i], carry[i+1] ); end endgenerateendmodule Use parameter for loop bounds6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 9Generate statements are useful for more than just module instantiationmodule adder#( parameter WIDTH = 1 )( input [WIDTH-1:0] op1,op2, output cout, output [WIDTH-1:0] sum ); wire [WIDTH:0] carry; assign carry[0] = 1’b0; assign cout = carry[WIDTH]; genvar i; generate for ( i = 0; i < WIDTH; i = i+1 ) begin : ripple assign {carry[i+1],sum[i]} = op1[i] + op2[i] + carry[i]; end endgenerateendmodule Statically elaborating many continuous assignments6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 10Traditionally designers have resorted to behavioral inference for elaborationmodule adder#( parameter WIDTH = 1 ) ( input [WIDTH-1:0] op1,op2, output cout, output reg [WIDTH-1:0] sum ); wire [WIDTH:0] carry; assign cout = carry[WIDTH]; integer i; always @(*) begin assign carry[0] = 1’b0; for ( i = 0; i < WIDTH; i = i+1 ) {carry[i+1],sum[i]} = op1[i] + op2[i] + carry[i]; end endendmoduleAlthough similar to generate block, this code has very different semantics!6.375 Spring 2006 • L03 Verilog 2 -
View Full Document
Unlocking...