1March 7, 2008 L12-1http://csg.csail.mit.edu/6.375Multiple Clock DomainsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyBased on material prepared by Bluespec IncMarch 7, 2008 L12-2http://csg.csail.mit.edu/6.375802.11 Transmitter OverviewController Scrambler EncoderInterleaver MapperIFFTCyclicExtendheadersdataClock frequencies: f/52ff/13The relative clock frequency of each block is based on its internal architecture and the overall performance requirement2March 7, 2008 L12-3http://csg.csail.mit.edu/6.375Synthesis results for different microachitectures408 ns24 ns7 ns15nsThroughput (1 symbol)8 ns8 ns7 ns15 nsCLK Period0.230.831.46 1.03Area (mm2)S Folded1 RadixFoldedPipelinedComb.Design408 ns24 ns21 ns15 nsLatencyTSMC .13 micron; numbers reported are before place and route.Single radix-4 node design is ¼ the size of combination design but still meets the throughput requirement easily; clock can reduced to 15 to 20 MhzNirav Dave Mike PellauerMan C NgWill have to run ~20 times faster for the same throughputMarch 7, 2008 L12-4http://csg.csail.mit.edu/6.375BSV point of viewAutomate the simplest thingsMake it easy to do simple thingsMake it safe to do the more complicated things3March 7, 2008 L12-5http://csg.csail.mit.edu/6.375The simplest caseOnly one clockNeed never be mentioned in BSV source (Note: hasn’t been mentioned in any examples so far!)Synthesized modules have an input port called CLKThis is passed to all interior instantiated modulesMarch 7, 2008 L12-6http://csg.csail.mit.edu/6.375Multiple Clock Domains in BluespecThe Clock type, and functions ←Clock familiesMaking clocksMoving data across clock domainsRevisit the 802.11a Transmitter4March 7, 2008 L12-7http://csg.csail.mit.edu/6.375The Clock typeClock is an ordinary first-class typeMay be passed as parameter, returned as result of function, etc.Can make arrays of them, etc.Can test whether two clocks are equalClock c1, c2;Clock c = (b ? c1 : c2); // b must be known atcompile timeMarch 7, 2008 L12-8http://csg.csail.mit.edu/6.375The Clock typeConceptually, a clock consists of two signals an oscillator a gating signalIn general, implemented as two wiresIf ungated, oscillator is running Whether the oscillator is running when it is gated off depends on implementation library—tool doesn’t care5March 7, 2008 L12-9http://csg.csail.mit.edu/6.375Instantiating moduleswith non-default clocksExample: instantiating a register with explicit clockModules can also take clocks as ordinary arguments, to be fed to interior module instantiationsClock c = … ;Reg# (Bool) b <- mkReg (True, clocked_by c);March 7, 2008 L12-10http://csg.csail.mit.edu/6.375The clockOf() functionMay be applied to any BSV expression, and returns a value of type ClockIf the expression is a constant, the result is the special value noClockThe result is always well-defined Expressions for which it would not be well-defined are illegal6March 7, 2008 L12-11http://csg.csail.mit.edu/6.375The clockOf() functionExamplec, c1 and c2 are all equalThey may be used interchangeably for all purposesReg# (UInt# (17)) x <- mkReg (0, clocked_by c);let y = x + 2;Clock c1 = clockOf (x);Clock c2 = clockOf (y);March 7, 2008 L12-12http://csg.csail.mit.edu/6.375A special clockEach module has a special “default” clockThe default clock will be passed to any interior module instantiations (unless otherwise specified)It can be exposed in any module as follows:Clock c <- exposeCurrentClock;7March 7, 2008 L12-13http://csg.csail.mit.edu/6.375Multiple Clock Domains in BluespecThe Clock type, and functions √Clock families ←Making clocksMoving data across clock domainRevisit the 802.11a TransmitterMarch 7, 2008 L12-14http://csg.csail.mit.edu/6.375Clock familiesAll clocks in a “family” share the same oscillator They differ only in gatingIf c2 is a gated version of c1, we say c1 is an “ancestor” of c2 If some clock is running, then so are all its ancestorsThe functions isAncestor(c1,c2) and sameFamily(c1,c2) are provided to test these relationships Can be used to control static elaboration (e.g., to optionally insert or omit a synchronizer)8March 7, 2008 L12-15http://csg.csail.mit.edu/6.375Clock family disciplineAll the methods invoked by a rule (or by another method) must be clocked by clocks from one family The tool enforces thisThere is no need for special domain-crossing logic when the clocks involved are from the same family It’s all handled by implicit conditionsMarch 7, 2008 L12-16http://csg.csail.mit.edu/6.375Clocks and implicit conditionsEach action is implicitly guarded by its clock’s gate; this will be reflected in the guards of rules and methods using that action So, if the clock is off, the method is unready So, a rule can execute only if all the methods it uses have their clocks gated onThis doesn’t happen for value methods So, they stay ready if they were ready when the clock was switched off9March 7, 2008 L12-17http://csg.csail.mit.edu/6.375Clocks and implicit conditionsExample:If c is switched off: f.enq, f.deq and f.clear are unready f.first remains ready if the fifo was non-empty when the clock was switched offFIFO #(Int #(3)) f <- mkFIFO (clocked_by c);March 7, 2008 L12-18http://csg.csail.mit.edu/6.375The clocks of methods and rulesEvery method, and every rule, has a notional clockFor methods of primitive modules (Verilog wrapped in BSV): Their clocks are specified in the BSV wrappers which import themFor methods of modules written in BSV: A method’s clock is a clock from the same family as the clocks of all the methods that it, in turn, invokes The clock is gated on if the clocks of all invoked methods are gated on If necessary, this is a new clockThe notional clock for a rule may be calculated in the same way10March 7, 2008 L12-19http://csg.csail.mit.edu/6.375Multiple Clock Domains in BluespecThe Clock type, and functions √Clock families √Making clocks ←Moving data across clock domainRevisit the 802.11a TransmitterMarch 7, 2008 L12-20http://csg.csail.mit.edu/6.375Making gated clocksc0 is a version of the current clock, gated by b c0’s gate is the gate of the current clock AND’ed with b The current clock is an ancestor of c0Bool b = … ;Clock c0 <- mkGatedClock (b);11March 7, 2008 L12-21http://csg.csail.mit.edu/6.375Making gated clocksc1 is a version of c0, gated by b1 and is also a version of the current clock, gated by
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