Verilog 2 - Design Examples6.375 Complex Digital SystemsChristopher BattenFebruary 13, 20066.375 Spring 2006 • L03 Verilog 2 - Design Examples • 2Course administrative notes• If you did not receive an email over the weekend concerning the course then you are not on the student mailing list - please email 6.375-staff• Lab 1 has been posted on the course website. It is due Friday, February 24– 2-stage SMIPSv2 processor RTL checked into CVS– Critical thinking questions• Tutorials on VCS, CVS, and SMIPS assembly programming will be posted this week6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 3Verilog Design Examples• Parameterized Static Elaboration• Greatest Common Divisor• Unpipelined SMIPSv1 processor6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 4Static elaboration enables generation of hardware at synthesis timeRegisterTransfer LevelGate LevelAuto Place + RouteTestResultsSimulateElaboratedDesignLogic SynthesisStatic ElaborationTestResultsSimulateWe will look at two forms of static elaboration: (1) parameters and (2) generate blocks6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 5Parameters are bound during static elaboration creating flexible modulesmodule vcMux2#( parameter WIDTH = 1 )( input [WIDTH-1:0] in0, in1,input [1:0] sel,output [WIDTH-1:0] out );always @(*)begincase ( sel )1’d0 : out = in0;1’d1 : out = in1;default : out = {WIDTH{1’bx}};endcaseendendmoduleInstantiation SyntaxvcMux2#(32) alu_mux( .in0 (op1), .in1 (bypass), .sel (alu_mux_sel),.out (alu_mux_out) );6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 6Parameters are bound during static elaboration creating flexible modulesmodule vcERDFF_pf#( parameter WIDTH = 1, parameter RESET_VALUE = 0 )( input clk,input reset,input [WIDTH-1:0] d,input en,output reg [WIDTH-1:0] q );always @( posedge clk )if ( reset )q <= RESET_VALUE;else if ( en )q <= d;endmoduleInstantiation SyntaxvcERDFF_pf#(32,32’h10) pc_pf( .clk (clk),.reset (reset),.en (pc_enable),.d (pc_mux_out),.q (pc));6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 7Generate blocks can execute loops and conditionals during static elaborationmodule adder ( input [3:0] op1,op2,output cout,output [3:0] sum );wire [4:0] carry;assign carry[0] = 1’b0;assign cout = carry[4]genvar i;generatefor ( i = 0; i < 4; i = i+1 )begin : rippleFA fa( op1[i], op2[i], carry[i], carry[i+1] );endendgenerateendmoduleAll genvars must be disappear after static elaborationGenerated names will have ripple[i]. prefix6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 8Combining parameters + generate blocks enables more powerful elaborationmodule adder#( parameter WIDTH = 1 )( input [WIDTH-1:0] op1,op2,output cout,output [WIDTH-1:0] sum );wire [WIDTH:0] carry;assign carry[0] = 1’b0;assign cout = carry[WIDTH];genvar i;generatefor ( i = 0; i < WIDTH; i = i+1 )begin : rippleFA fa( op1[i], op2[i], carry[i], carry[i+1] );endendgenerateendmoduleUse parameter for loop bounds6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 9Generate statements are useful for more than just module instantiationmodule adder#( parameter WIDTH = 1 )( input [WIDTH-1:0] op1,op2,output cout,output [WIDTH-1:0] sum );wire [WIDTH:0] carry;assign carry[0] = 1’b0;assign cout = carry[WIDTH];genvar i;generatefor ( i = 0; i < WIDTH; i = i+1 )begin : rippleassign {carry[i+1],sum[i]} = op1[i] + op2[i] + carry[i];endendgenerateendmoduleStatically elaborating many continuous assignments6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 10Traditionally designers have resorted to behavioral inference for elaborationmodule adder#( parameter WIDTH = 1 ) ( input [WIDTH-1:0] op1,op2,output cout,output reg [WIDTH-1:0] sum );wire [WIDTH:0] carry;assign cout = carry[WIDTH];integer i;always @(*)beginassign carry[0] = 1’b0;for ( i = 0; i < WIDTH; i = i+1 ){carry[i+1],sum[i]} = op1[i] + op2[i] + carry[i];endendendmoduleAlthough similar to generate block, this code has very different semantics!6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 11Verilog Design Examples• Parameterized Static Elaboration• Greatest Common Divisor• Unpipelined SMIPSv1 processor6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 12Behavioral GCD model is written within a single always block with C like structuremodule gcdGCDUnit_behav#( parameter W = 16 )( input [W-1:0] inA, inB,output [W-1:0] out );reg [W-1:0] A, B, out, swap;integer done;always @(*)begindone = 0;A = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endout = A;endendmoduleTest harness will simply set the input operands and check the output.6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 13Simple test harness for behavioral model of GCDmodule exGCDTestHarness_behav;reg [15:0] inA, inB;wire [15:0] out;exGCD_behav#(16) gcd_unit( .inA(inA), .inB(inB), .out(out) );initialbegin// 3 = GCD( 27, 15 ) inA = 27;inB = 15;#10;if ( out == 3 )$display( "Test ( gcd(27,15) ) succeeded, [ %x == %x ]", out, 3 );else$display( "Test ( gcd(27,15) ) failed, [ %x != %x ]", out, 3 );$finish;endendmodule6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 14Behavioral GCD model is written within a single always block with C like structuremodule gcdGCDUnit_behav#( parameter W = 16 )( input [W-1:0] inA, inB,output [W-1:0] Y );reg [W-1:0] A, B, Y, swap;integer done;always @(*)begindone = 0;A = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endY = A;endendmoduleOur goal now is to design an RTL hardware block which implements this high-level behavior. What does the RTL implementation need?StateLess-Than ComparatorEqual ComparatorSubtractor6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 15The first step is to carefully design an appropriate port interfaceoperands_rdyoperands_valoperands_bits_Aoperands_bits_Bresult_bits_dataresult_rdyresult_valclk reset6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 16Next develop a datapath which has the proper functional units BA = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endY = A;zero? ltA6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 17Next develop a datapath which has the proper functional unitsBA = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone
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