Simulating Verilog RTL using Synopsys VCS6.375 Tutorial 1February 1, 2008In this tutorial you will gain experience using Synopsys VCS to compile cycle-accurate executablesimulators from Verilog RTL. You will also learn how to use the Synopsys Wavef orm viewer totrace the various signals in your design. Figure 1 illustrates the basic VCS and SMIPS assemblertoolflow. VCS takes a set of Verilog files as input and produces a simulator. When we execute thesimulator we need some way to observe our design so that we can measure its performance andverify that it is wor king correctly. There are two primary ways to observe our design: (1) we canuse $display statements in our Verilog RTL to output textual trace information, or (2) we caninstruct the simulator to automatically write transition information about each signal in our d esignto a file. There is s tandard text format for this type of signal transition trace information calledthe Value Change Dump format (VCD). Unfortunately, these textual trace fi les can become verylarge very quickly, so Synopsys uses a proprietary compressed b inary trace format called VCD Plus(VPD). We can view VPD files using the Synopsys waveform viewer called VirSim.We will be us ing a simple unpipelined SMIPSv1 processor as our design example for this tutorial,and thus you will also learn the how to build and run test codes on the processor simulator . Figure 2shows the block diagram for the example processor. Figure 1 shows the SMIPS assembler toolflowwhich starts with an SMIPS assemb ly file and uses several tools to generate a Verilog Memory Hex(VMH) file suitable to run on the cycle-accurate simulator. This tutorial assumes you are familiarwith the SMIPS ISA. For more inform ation please consult the SMIPS Processor Specification.For more information consult the CVS user manual (cvs-user-guide.pdf) located in the courselocker (/mit/6.375/doc).Getting startedBefore using the 6.375 toolflow you must add the course locker and run the course setup script withthe following two commands.% add 6.375% source /mit/6.375/setup.csh6.375 Tutorial 1, Spring 2008 2VCSVerilogSourceVerilogLibsExecute SimVPDTraceTextOutputVirSimCycleSimAccurateObjDumpobjdump2vmh.plASMSourceCodeSMIPSBinarysmips-objdumpVMHsmips-testbuildFigure 1: VCS and SMIPS Assembler Toolflow6.375 Tutorial 1, Spring 2008 3For this tutorial we will be using an unpipelined SMIPSv 1 processor as our example RTL design.You should create a working directory and checkout the SMIPSv1 example project from the courseCVS repository using the following commands.% mkdir tut1% cd tut1% cvs checkout examples/smipsv1-1stage-v% cd examples/smipsv1-1stage-vBefore starting, take a look at the s ubdirectories in the smips1-1stage-v p roject d irectory. All ofour projects will have a similar structure. Source RTL should be placed in the src directory and testinput files should be placed in the tests directory. The build directory will contain all generatedcontent including simulators, synthesized gate-level Verilog, and final layout. In this course wewill always try to keep generated content separate from our source RTL. This keeps our proj ectdirectories well organized, and helps prevent us from unintentionally modifying our source RTL.There are subdirectories in the build directory for each major step in the 6.375 toolflow. Thesesubdirectories will contain scripts and configuration files necessary for running the tools requiredfor that step in the toolflow. For example, the build/vcs-sim-rtl directory contains a makefilewhich can bu ild Verilog simulators and run tests on these simulators . You should browse the sourceco de for the processor in src to become familiar with the design. The example code makes useof the simple Verilog component library (VCLIB) located in /mit/6.375/install/vclib. VCLIBincludes a variety of muxes, flip-flops, latches, RAMs, m emories, and queues. You are welcome toeither use VCLIB in your own projects or to create your own component library.rd0rd1RegFile>> 2SignExtendir[15:0]RegFileDataMemvalrwCmpeq?Instruction Memvalpc+4branch+4DecoderControlSignalstohosttohost_entestrig_tohostir[25:21]ir[20:16]Addwdataaddrrdatarf_wenwb_selir[20:16]PCpc_selFigure 2: Block diagram for Unp ipelined SMIPSv1 Processor6.375 Tutorial 1, Spring 2008 4Compiling the SimulatorIn this section we will first see h ow to run VCS from the command line, and then we will see howto automate the process usin g a makefile. To build the simulator we need to ru n the vcs compilerwith the appropriate command line arguments and a list of input verilog files.% pwdexamples/smipsv1-1stage-v% cd build/vcs-sim-rtl% vcs -PP +lint=all +v2k -timescale=1ns/10ps \-v /mit/6.375/install/vclib/vcDecoders.v \-v /mit/6.375/install/vclib/vcMuxes.v \-v /mit/6.375/install/vclib/vcArith.v \-v /mit/6.375/install/vclib/vcStateElements.v \-v /mit/6.375/install/vclib/vcMemories.v \../../src/smipsInst.v \../../src/smipsProcCtrl.v \../../src/smipsProcDpathRegfile.v \../../src/smipsProcDpath_pstr.v \../../src/smipsProc.v \../../src/smipsTestHarness.vBy default, VCS generates a simulator named simv. The -PP command line argument turns onsupport for using the VPD trace output format. The +lint=all argument turns on Verilog warnings.Since it is relatively easy to write legal Verilog code which is probably functionally incorrect, youwill always want to use this argument. For example, VCS will war n you if you connect nets withdifferent bitwidths or forget to wire up a port. Always try to eliminate all VCS compilation errorsand warnings. Since we will be making use of various Verilog-2001 language features, we need toset the +v2k command line option so that VCS will correctly handle these new constructs. Verilogallows a designer to specify how the abstract delay units in their design map into r eal time unitsusing the ‘timescale compiler directive. To make it easy to change this parameter we will specifyit on the command line instead of in the Verilog source. After these arguments we list the Verilogsource fi les. We use the -v flag to indicate which Verilog files are part of a library (and thus shouldonly be compiled if needed) and which files are part of the actual design (and thus should alwaysbe compiled). Af ter running this command, you should see text outp ut indicating that VCS isparsing the Verilog fi les and compiling the modules. Notice that VCS actually generates ANSI Cco de which is then compiled using gcc. When VCS is finished you should see a
View Full Document
Unlocking...