M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G YDEPARTMENT OF EL ECTRICAL ENGINEERING AND COMPUTER SCIENCE6.375 Complex Digital SystemsSpring 2006 - Quiz - March 24, 200680 MinutesNAME: SCORE:Please write your name on every page of the quiz.Not all questions are of equal difficulty, so look over the entire quiz and budget your time carefully.Please carefully state any assumptions you make.Enter your answers in the spaces provided below. If you need extra room for an answer or forscratch work, you may u se the back of each page but please clearly indicate where your answer islocated.A list of useful equations is printed at the end of this quiz. You can detach this sheet for referenceand do not have to hand this in. We will not grade anything written on the equation sheet.You will also receive a separate handout containing a copy of the relevant Bluespec lecture slidesand code. We will not grade anything written on the Bluespec slides.You must not discuss the quiz’s contents with other students who have not yet takenthe quiz. If, prior to taking it, you are inadvertently exposed to material in a quiz —by whatever means — you must immediately inform the instructor or a TA.Points ScoreProblem 1 25Problem 2 25Problem 3 25Problem 4 256.375 Quiz, Spring 2006 Name: 2Problem 1 : Logical Effort for Incrementer Carry Chain (25 total points)The following diagram illustrates two different incrementer architectures. For all parts of thisquestion you should assume that the delay unit (τ) for this process is 10 ps and that the parasiticdelay of a minimum-sized inverter (Pinv) is 1.sum[0]sum[1]sum[2]sum[3]sum[4]sum[5]sum[6]sum[7]in[0]in[1]in[7] in[6] in[5] in[4] in[3] in[2]Ripple-Carry Architecturesum[1]sum[2]sum[3]sum[4]sum[5]sum[6]sum[7] sum[0]in[1]in[2]in[3]in[4]in[5]in[6]in[7]in[0]in[1]in[6] in[5] in[4] in[3] in[2]Parallel-Prefix ArchitecturePart 1.A : Critical paths for the adder architectures (5 points)Draw a line through the critical path for both the r ipple-carry and the parallel-prefix architectures.When determining the critical path you can assume that XOR gates are slower than NAND/NORgates which are slower than inverters.6.375 Quiz, Spring 2006 Name: 3Part 1.B : Optimal delay of the adder architectures (10 points)Use logical effort to calculate the optimal delay of the critical path for both architectures in picosec-onds. You should ignore all gates which are not on the critical path! Do not using branching effort.Ignore the fact that some gates have a fanout greater than one. The desired input capacitance ofthe isolated carry chain is 6 fF (since we are ignoring gates which are not on the critical path this isthe input capacitance for a single gate). The load capacitance of every sum output is 60 fF. Showall your work.Part 1.C : Gate sizing for the a dder architectures (10 points)Identify the optimum gate sizes for each gate in the critical path for both architectures. The gatesizes should be in femtofarads of input capacitance.6.375 Quiz, Spring 2006 Name: 4Problem 2 : RC Modeling of Register File Write Bitline (25 total points)In this problem we will be revisiting the register file write bitline you analyzed in Lab 2. Rememberthat the write bitline must drive the D input port of 32 flip-fl ops. The combined gate capacitanceof these flip-flops can be a significant load on the write bitline. The load on the write bitline isfurther increased by wire capacitance, since flip-flops are usually large and thus often spread apart.The following figure illustrates th e wr ite bitline including a reasonable final stage of the bitlinedriver. For this problem we will only consider this final stage even though the real driver mightinclude many stages. As you determined in the lab assignment, each bitcell is 15.68 µm wide andthe input capacitance of the bitcell’s D port is 3 fF. The following figur e illustrates the register filewrite bitline. The bitline is routed on Metal 2. You can ignore any via resistance or capacitance.Remember that the driver PMOS/NMOS sizes are in units of minimum NMOS transistor width(0.36 µm). For example, the NMOS for the last stage of the bitline driver is 0.36 µm × 32 =11.52 µm.Input (D) Port (3fF)Bit-Cell15.68um15.68um10 23264Last Driver StageWrite Bit-Line31The following table lists various parameters for a 0.18 µm technology which you may find usefulwhen s olving this problem. Remember that there is a list of equations at the end of this quiz.Transistor Process Parameters ValueDesired ratio of PMOS/NMOS widths 2PMOS gate capacitance per µm of transistor width 1.5 fF/µmNMOS gate capacitance per µm of transistor width 1.5 fF/µmPMOS drain capacitance per µm of transistor width 0.3 fF/µmNMOS drain capacitance per µm of transistor width 0.3 fF/µmPMOS effective on resistance 6.6 kΩµmNMOS effective on resistance 3.3 kΩµmParameters for Metal 2 WireValueWire resistance per unit length 0.4 Ω/µmWire capacitance per unit length 0.2 fF/µm6.375 Quiz, Spring 2006 Name: 5Part 2.A : Delay calculation with end-of-line driver (10 points)Draw a simple RC model for the register file wr ite bitline. Only include the final stage of the driver.Use a lumped π wire model. Use the RC model to determine the delay of the write bitline. Expressyour answer in RC time constants. This part is very similar to the qu estion asked in Lab 2.6.375 Quiz, Spring 2006 Name: 6Part 2.B : Delay calculation w ith middle-line driver (15 points)There is no reason we have to position the write bitline driver at one end of the bitline. In thispart we will evaluate moving the driver to the middle of the b itline. The following figure illustratesthe new design.3116326415.68um10 2 15Last Driver StageDraw a new RC model for the register file write bitline. Use the RC model to determine the delayof the write bitline. Express your answer in RC time constants. How does this new design compareto the baseline design evaluated in Part 2.A? Do es this approach help mitigate wire resistance,wire capacitance, or both?6.375 Quiz, Spring 2006 Name: 7Problem 3 : Bluespec Synthesis (25 total points)Consider the algorithm for b inary multiplication presented in Lecture 7 (Introduction to Bluespec):1001 // d = 4’d9x 0101 // r = 4’d5---------1001 // d << 0 (since r[0] == 1)0000 // 0 << 1 (since r[1] == 0)1001 // d << 2 (since r[2] == 1)0000 // 0 << 3 (since r[3] == 0)---------0101101 // product (sum of above) = 45This algorithm is actually quite similar to the software
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