Slide 1Why Multiple Clock DomainsClocks and Power802.11 TransmitterSynthesis results for different microachitecturesHow to take advantage of this: Clock DomainsThe simplest caseMultiple Clock Domains in BluespecThe Clock typeSlide 10Instantiating modules with non-default clocksThe clockOf() functionSlide 13A special clockSlide 15Clock familiesClock family disciplineClocks and implicit conditionsSlide 19The clocks of methods and rulesSlide 21Making gated clocksSlide 23More Clock constructorsClock DividersSlide 26Slide 27Moving Data Across Clock DomainsSynchronizers2 - Flop SynchronizerBluespec’s 2-Flop SynchronizerSmall ExampleAdding the SynchronizerFull ExampleOther SynchronizersSlide 36802.11 Transmitter OverviewThe TransmitterSlide 39The Transmitter (after)Clock Domain CrossingDid not work...The Fix – pass the clocks outSummaryMarch 4, 2009 L13-1http://csg.csail.mit.edu/6.375Multiple Clock DomainsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyBased on material prepared by Bluespec IncMarch 4, 2009 L13-2http://csg.csail.mit.edu/6.375Why Multiple Clock DomainsArise naturally in interfacing with the outside worldNeeded to manage clock skewAllow parts of the design to be isolated to do selective power gating and clock gatingReduce power and energy consumptionMarch 4, 2009 L13-3http://csg.csail.mit.edu/6.375Clocks and Power Power 1/2CV2fEnergy 1/2CV2Power can be lowered by either lowering the voltage or frequencyFrequency has some indirect effect in reducing energy (allows smaller/fewer gates)March 4, 2009 L13-4http://csg.csail.mit.edu/6.375802.11 TransmitterController Scrambler EncoderInterleaver MapperIFFTCyclicExtendheadersdataClock speed ff/13f/52After the design you may discover the clocks of many boxes can be lowered without affecting the overall performanceMarch 4, 2009 L13-5http://csg.csail.mit.edu/6.375Synthesis results for different microachitecturesDesignArea (mm2) Best CLK PeriodThroughput CLK/symbol LatencyComb. 1.03 15 ns 1 15 nsPipelined 1.46 7 ns 1 21 nsFolded 0.83 8 ns 3 24 nsS Folded1 Radix0.23 8 ns 48-51 408 nsTSMC .13 micron; numbers reported are before place and route.Single radix-4 node design is ¼ the size of combinational design but still meets the throughput requirement easily; clock can be reduced to 15 - 20 MhzDave,Pellauer,Ng 2005For the same throughput SF has to run ~16 times faster than FMarch 4, 2009 L13-6http://csg.csail.mit.edu/6.375How to take advantage of this: Clock DomainsBSV point of view on clocksAutomate the simplest thingsMake it easy to do simple thingsMake it safe to do the more complicated thingsMarch 4, 2009 L13-7http://csg.csail.mit.edu/6.375The simplest caseOnly one clockNeed never be mentioned in BSV source(Note: hasn’t been mentioned in any examples so far!)Synthesized modules have an input port called CLKThis is passed to all interior instantiated modulesMarch 4, 2009 L13-8http://csg.csail.mit.edu/6.375Multiple Clock Domains in BluespecThe Clock type, and functions Clock familiesMaking clocksMoving data across clock domainsRevisit the 802.11a TransmitterMarch 4, 2009 L13-9http://csg.csail.mit.edu/6.375The Clock typeClock is an ordinary first-class typeMay be passed as parameter, returned as result of function, etc.Can make arrays of them, etc.Can test whether two clocks are equal (at compile time only)Clock c1, c2;Clock c = (b ? c1 : c2); // b must be known at compile timeMarch 4, 2009 L13-10http://csg.csail.mit.edu/6.375The Clock typeConceptually, a clock consists of two signalsan oscillatora gating signalIn general, implemented as two wiresIf ungated, oscillator is runningWhether the oscillator is running when it is gated off depends on implementation library—tool doesn’t careMarch 4, 2009 L13-11http://csg.csail.mit.edu/6.375Instantiating moduleswith non-default clocksExample: instantiating a register with explicit clockModules can also take clocks as ordinary arguments, to be fed to interior module instantiationsClock c = … ;Reg# (Bool) b <- mkReg (True, clocked_by c);March 4, 2009 L13-12http://csg.csail.mit.edu/6.375The clockOf() functionMay be applied to any BSV expression, and returns a value of type ClockIf the expression is a constant, the result is the special value noClockThe result is always well-definedExpressions for which it would not be well-defined are illegalMarch 4, 2009 L13-13http://csg.csail.mit.edu/6.375The clockOf() functionExamplec, c1 and c2 are all equalThey may be used interchangeably for all purposesReg# (UInt# (17)) x <- mkReg (0, clocked_by c);let y = x + 2;Clock c1 = clockOf (x);Clock c2 = clockOf (y);March 4, 2009 L13-14http://csg.csail.mit.edu/6.375A special clockEach module has a special “default” clockThe default clock will be passed to any interior module instantiations (unless otherwise specified)It can be exposed in any module as follows:Clock c <- exposeCurrentClock;March 4, 2009 L13-15http://csg.csail.mit.edu/6.375Multiple Clock Domains in BluespecThe Clock type, and functions √Clock families Making clocksMoving data across clock domainRevisit the 802.11a TransmitterMarch 4, 2009 L13-16http://csg.csail.mit.edu/6.375Clock familiesAll clocks in a “family” share the same oscillatorThey differ only in gatingIf c2 is a gated version of c1, we say c1 is an “ancestor” of c2If some clock is running, then so are all its ancestorsThe functions isAncestor(c1,c2) and sameFamily(c1,c2) are provided to test these relationshipsCan be used to control static elaboration (e.g., to optionally insert or omit a synchronizer)March 4, 2009 L13-17http://csg.csail.mit.edu/6.375Clock family disciplineAll the methods invoked by a rule (or by another method) must be clocked by clocks from one familyThe tool enforces thisThe rule will fire only when the clocks of all the called methods are ready (their gates are true)Two different clock families can interact with each other only though some clock synchronizing state element, e.g., FIFO, registerMarch 4, 2009 L13-18http://csg.csail.mit.edu/6.375Clocks and implicit conditionsEach action is implicitly guarded by its clock’s gate; this will be reflected in the guards of rules and methods using that action So, if the clock is off, the method is unreadySo, a rule can execute only if all the methods it uses have their clocks gated onThis doesn’t happen for value methodsSo, they stay ready if they were
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