1February 6, 2008 http://csg.csail.mit.edu/6.375/ L01-16.375 Complex Digital SystemSpring 2008Lecturers: ArvindTA: Abhinav AgrawalAssistant: Sally LeeFebruary 6, 2008 L01-2http://csg.csail.mit.edu/6.375/Do we need more chips (ASICs)?ASIC=Application-Specific Integrated Circuit2February 6, 2008 L01-3http://csg.csail.mit.edu/6.375/Wide Variety of Products Rely on ASICsFebruary 6, 2008 L01-4http://csg.csail.mit.edu/6.375/Source: http://www.intel.com/technology/silicon/mooreslaw/index.htmWhat’s required?ICs with dramatically higher performance, optimized for applicationsand at a size and power to deliver mobilitycost to address mass consumer markets3February 6, 2008 L01-5http://csg.csail.mit.edu/6.375/Let’s take a look at current CMOS technology...February 6, 2008 L01-6http://csg.csail.mit.edu/6.375/FET = Field-Effect TransistorA four terminal device (gate, source, drain, bulk)Inversion: A vertical field creates a channel between the source and drain.Conduction: If a channel exists, a horizontal field causes a drift current from the drain to the source.EhEvSource diffusionDrain diffusiongatebulkSurface of waferReverse side of waferinversionhappens here4February 6, 2008 L01-7http://csg.csail.mit.edu/6.375/Simplified FET ModelGPFET connects S and D when G=“low”=0VGNFET connects D and S when G=“high”=VDDSDSDGPFET only good at pulling upGNFET only good at pulling downSupply Voltage = VDDGround = GND = 0VBinary logic values represented by voltages:“High” = Supply Voltage, “Low” = Ground VoltageFebruary 6, 2008 L01-8http://csg.csail.mit.edu/6.375/NAND GateAB(A.B) When both A and B are high, output is low When either A or B is low, output is highBA(A.B)5February 6, 2008 L01-9http://csg.csail.mit.edu/6.375/NAND Gate LayoutAB(A.B)Series NMOS TransistorsParallel PMOS TransistorsMetal 1-Diffusion ContactP-Diffusion (in N-well)N-DiffusionGNDVDDAB(A.B)Poly wire connects PMOS & NMOS gatesOutput on Metal-1February 6, 2008 L01-10http://csg.csail.mit.edu/6.375/Chip = Transistors + WiresCross-section through IBM 90nm process, 10 metal layersw[ISSCC 2004] Transistors fabricated first on original surface of waferThicker wires on higher layers used for power and ground, and long range signalsThinner wires on lower layers used for dense local wiringBulk of wafer“Vias” connect one layer to another“Glass” on top seals chipWiring added in layers on top of wafer6February 6, 2008 L01-11http://csg.csail.mit.edu/6.375/Exponential growth: Moore’s LawIntel 8080A, 19743Mhz, 6K transistors, 6uIntel 8086, 1978, 33mm210Mhz, 29K transistors, 3uIntel 80286, 1982, 47mm212.5Mhz, 134K transistors, 1.5uIntel 386DX, 1985, 43mm233Mhz, 275K transistors, 1u Intel 486, 1989, 81mm250Mhz, 1.2M transistors, .8uIntel Pentium, 1993/1994/1996, 295/147/90mm266Mhz, 3.1M transistors, .8u/.6u/.35uIntel Pentium II, 1997, 203mm2/104mm2300/333Mhz, 7.5M transistors, .35u/.25uhttp://www.intel.com/intel/intelis/museum/exhibit/hist_micro/hof/hof_main.htmShown with approximate relative sizesShown with approximate relative sizesFebruary 6, 2008 L01-12http://csg.csail.mit.edu/6.375/Intel Penryn (2007)Dual coreQuad-issue out-of-order superscalar processors6MB shared L2 cache45nm technology Metal gate transistors High-K gate dielectric410 Million transistors3+? GHz clock frequencyCould fit over 500 486 processors on same size die.7February 6, 2008 L01-13http://csg.csail.mit.edu/6.375/But Design Effort is GrowingNvidia Graphics Processing Units02040608010012019931995199619971998199920002001200120022002Design Effort per Chip Transistors (M)Relative staffing on front-endRelative staffing on back-end9x growth in back-end staff5x growth in front-end staffFront-end is designing the logic (RTL)Back-end is fitting all the gates and wires on the chip; meeting timing specifications; wiring up power, ground, and clockFebruary 6, 2008 L01-14http://csg.csail.mit.edu/6.375/Design Cost Impacts Chip Cost90nm ASIC cost breakdown, $30M total (Altera study): 59% chip design (architecture, logic & I/O design, product & test engineering) 30% software and applications development 11% prototyping (masks, wafers, boards)If we sell 100,000 units, Non-Recurring Engineering (NRE) costs add $30M/100K = $300 per chip!Example above is for design using automated tools Similar to what we’ll be using in 6.375Hand-crafted IBM-Sony-Toshiba Cell microprocessor achieves 4GHz in 90nm, but development cost was >$400M8February 6, 2008 L01-15http://csg.csail.mit.edu/6.375/Topics to address in 6.375How can we design complex billion transistor ASICs with reasonable effort?How good are our designs? Performance, area, powerFebruary 6, 2008 L01-16http://csg.csail.mit.edu/6.375/Designer’s DilemmaSub-optimal implementations!Designer must take shortcuts Conservative design No time for exploration Educated guess & code Gates are free mentalityConstants 10-30 person design team size 18 month design schedule Design flow -- unchanged for 10+ years!ASIC Complexity 2000: 1M+ logic gates 2005: 10M+ logic gates 2010: 100M+ logic gates63.53.322,391Static (2)99.999.963.5MemoryUtil (%)3.608,898Static4.7015,910Linear3.678,170CircularSpeed(ns)Area(gates)LPM PipelineWhat happens when a designer must implement a 1M gate block?Alternatives?[ICCAD’04]LPM Pipeline example: Which is best?9February 6, 2008 L01-17http://csg.csail.mit.edu/6.375/6.375 Course PhilosophyEffective abstractions to reduce design effort High-level design language rather than logic gates Control specified with Guarded Atomic Actions rather than with finite state machines Guarded module interfaces automatically ensure correctness of composition of existing modulesDesign discipline to avoid bad design points Decoupled units rather than tightly coupled state machinesDesign space exploration to find good designs Architecture choice has largest impact on solution qualityA unified view of languages, disciplines and tools that supports rapid design space exploration to find best area, power, and performance point with reduced design effortFebruary 6, 2008 L01-18http://csg.csail.mit.edu/6.375/6.375 ObjectivesBy end of term, you should be able to:Decompose system requirements into a hierarchy of sub-units that are easy to specify, implement, and verify, and which can be reusedDevelop efficient verification and test plansSelect appropriate microarchitectures for a unit and perform microarchitectural exploration to meet price,
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