1Verilog 2 - Design Examples6.375 Complex Digital SystemsFebruary 11, 20086.375 Spring 2008 • L03 Verilog 2 • 2Verilog can be used at several levelsautomatic tools to synthesize a low-level gate-level model.High-Level BehavioralRegister Transfer Level Gate Level A common approach is to use C/C++ for initial behavioral modeling, and for building test rigs.26.375 Spring 2008 • L03 Verilog 2 • 3Writing Good Synthesizable Verilog• Use only positive-edge triggered flip-flops for state• Do not assign the same variable from more than one always block• Describe combinational logic using continuous assignments (assign) and always@(*) blocks with blocking assignments (=) assign C_in = B_out + 1;always @(*)beginout = 2’d0; if (in1 == 1) out = 2’d1;else if (in2 == 1)out = 2’d2;end• Describe sequential logic using always @(posedge clk) and non-blocking assignments (<=)always @( posedge clk )C_out <= C_in;• Only leaf modules should have functionality; use higher-level modules only for wiring together sub-modules6.375 Spring 2008 • L03 Verilog 2 • 4wire A_in, B_in, C_in;reg A_out, B_out, C_out;always @( posedge clk )beginA_out <= A_in;B_out <= B_in;C_out <= C_in;endassign B_in = A_out + 1;assign C_in = B_out + 1;An example+1A+1B CThe order of non-blocking assignments does not matter!36.375 Spring 2008 • L03 Verilog 2 • 5Another style – multiple always blockswire A_in, B_in, C_in;reg A_out, B_out, C_out;always @( posedge clk )A_out <= A_in;assign B_in = A_out + 1;always @( posedge clk )B_out <= B_in;assign C_in = B_out + 1;always @( posedge clk )C_out <= C_in;+1A+1B CDoes it have the same functionality6.375 Spring 2008 • L03 Verilog 2 • 6Execution semantics of Verilogwire A_in, B_in, C_in;reg A_out, B_out, C_out;always @( posedge clk )A_out <= A_in;assign B_in = A_out + 1;always @( posedge clk )B_out <= B_in;assign C_in = B_out + 1;always @( posedge clk )C_out <= C_in;Active Event QueueA1B2COn clock edge all those events which are sensitive to the clock are added to the active event queue in any order!ABC46.375 Spring 2008 • L03 Verilog 2 • 7Semantics of non-blocking assignment requires two event queueswire A_in, B_in, C_in;reg A_out, B_out, C_out;always @( posedge clk )A_out <= A_in;assign B_in = A_out + 1;always @( posedge clk )B_out <= B_in;assign C_in = B_out + 1;always @( posedge clk )C_out <= C_in;Active Event QueueA1B2CNon-Blocking QueueARBRCR12ALBLCLVariables in RHS of always blocks are not updated until all inputs (e.g. LHS + dependencies) are evaluated6.375 Spring 2008 • L03 Verilog 2 • 8Behavioral Verilog is richer• Characterized by heavy use of sequential blocking statements in large always blocks• Many constructs are not synthesizable but can be useful for behavioral modeling– Data dependent for and while loops– Additional behavioral datatypes: integer, real– Magic initialization blocks: initial– Magic delay statements: #<delay>– System calls: $display, $assert, $finish56.375 Spring 2008 • L03 Verilog 2 • 9System tasks are used for test harnesses and simulation managementreg [ 1023:0 ] exe_filename; initialbegin// This turns on VCD (plus) output$vcdpluson(0);// This gets the program to load into memory from the command lineif ( $value$plusargs( "exe=%s", exe_filename ) )$readmemh( exe_filename, mem.m );elsebegin$display( "ERROR: No executable specified! (use +exe=<filename>)" );$finish;end// Stobe reset#0 reset = 1;#38 reset = 0;end6.375 Spring 2008 • L03 Verilog 2 • 10Verilog Design Examples• Greatest Common Divisor• Unpipelined SMIPSv1 processor66.375 Spring 2008 • L03 Verilog 2 • 11GCD in C int GCD( int inA, int inB) { int done = 0;int A = inA; int B = inB;while ( !done ){if ( A < B ){swap = A;A = B;B = swap;} else if ( B != 0 )A = A - B;elsedone = 1;}return A;}Such a GCD description can be easily written in Behavioral VerilogIt can be simulated but it will have nothing to do with hardware, i.e. it won’t synthesize.6.375 Spring 2008 • L03 Verilog 2 • 12Behavioral GCD in Verilogmodule gcdGCDUnit_behav#( parameter W = 16 )( input [W-1:0] inA, inB,output [W-1:0] out );reg [W-1:0] A, B, out, swap;integer done;always @(*)begindone = 0;A = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endout = A;endendmoduleUser simply sets the input operands and checks the output; the answer will appear immediately, like a combinational circuitData dependent loop, “done”76.375 Spring 2008 • L03 Verilog 2 • 13You have to be careful in using such behavioral modelsmodule exGCDTestHarness_behav;reg [15:0] inA, inB;wire [15:0] out;exGCD_behav#(16) gcd_unit( .inA(inA), .inB(inB), .out(out) );initialbegin// 3 = GCD( 27, 15 ) inA = 27;inB = 15;#10;if ( out == 3 )$display( "Test ( gcd(27,15) ) succeeded, [ %x == %x ]", out, 3 );else$display( "Test ( gcd(27,15) ) failed, [ %x != %x ]", out, 3 );$finish;endendmodulewithout some delay out is bogus6.375 Spring 2008 • L03 Verilog 2 • 14Deriving an RTL model for GCDmodule gcdGCDUnit_behav#( parameter W = 16 )( input [W-1:0] inA, inB,output [W-1:0] Y );reg [W-1:0] A, B, Y, swap;integer done;always @(*)begindone = 0;A = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endY = A;endendmoduleWhat does the RTL implementation need?StateLess-Than ComparatorEqual ComparatorSubtractor86.375 Spring 2008 • L03 Verilog 2 • 15The first step is to carefully design an appropriate port interfaceidleinput_availableoperands_bits_Aoperands_bits_Bresult_bits_dataresult_takenresult_rdyclk reset6.375 Spring 2008 • L03 Verilog 2 • 16Next develop a datapath which has the proper functional unitsBA = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endY = A;zero? ltAsub96.375 Spring 2008 • L03 Verilog 2 • 17Finally add the control unit to sequence the datapathBAmuxselAregenBmuxselBregenA < BB = 0A = inA; B = inB;while ( !done )beginif ( A < B )swap = A;A = B;B = swap;else if ( B != 0 )A = A - B;elsedone = 1;endY = A;zero? ltAsubControl unit should be designed so that it is either busy or waiting for input or waiting for out to be picked up6.375 Spring 2008 • L03 Verilog 2 • 18Datapath module interfacemodule gcdGCDUnitDpath_sstr#( parameter W = 16 )(input clk,// Data signalsinput [W-1:0] operands_bits_A, input [W-1:0] operands_bits_B, output [W-1:0] result_bits_data, // Control
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