ASIC Implementation of a Three-Stage SMIPSv2 Processor6.375 Laboratory 3Part IMarch 6, 2007In the first lab assignment, you built and tested an RTL model of a two-stage pipelined SMIPSv2processor while in the second lab, you built a Bluespec model of a 3 stage pipeline. In the third labassignment, you w ill be using various commercial EDA tools to synthesize, place, and route yourBluespec design. In add ition, you will attempt to optimize your design to increase performanceand/or decrease area. This lab has two objectives: the first is to introduce you to the tools you willbe using in your final projects and give you some intuition into how high-level hardware descriptionsare transformed into layout. The second objective is to deepen your understanding of Bluespecto the point where you can achieve full parallelism in your Bluespec designs. This will requireyou to fully grok what rule scheduling is all about, what makes rules conflict, and what semanticugliness we use to bypass the prob lem: RWIRES and EHR registers. CircBSV.tar, which is postedon the resour ces page of the course web-site, has some go od examples, though you may want touse the EHR elements from the course bluespec libr ary (/mit/6.375/install/bsvclib). Remember:RWire and its relatives polute the otherwise clean semantics of bluespec and while a solution to thisproblem of sequential rule composition has been proposed, it is not yet in the Bluespec compiler.The deliverables for this lab are (a) your optimized Bluespec source an d all of the scripts necessaryto completely generate you r ASIC implementation checked into CVS, and (b ) written answers tothe critical questions given at the end of this document. The lab assignment is due at the start ofclass on Friday, March 16. As usual, you must submit the written answers by hand in class.Before starting this lab, it is recommended that you r evisit the Bluespec model you wrote in thesecond lab. Take s ome time to clean up your code, add comments, and enforce a consistent namingscheme. You will find as you work through this lab assignment that having a more extensive modulehierarchy can be very advantageous; initially we will be preserving module boundaries throughoutthe toolflow which means that you will be able to obtain perf ormance and area results for eachmodule. Thus you might want to consider breaking your design into smaller pieces, allowing youto reason about performance of isolated components. By default, the Bluespec compiler flattensall module definitions into one large module. Use of the synthesize annotation before a moduleimplementation will direct BSC to generate modular verilog. P lease refer to the language referenceguide (/mit/6.375/doc/bsc-reference-guide.pdf) for more information on the use of this directive.Unfortunately, p reserving the module hierarchy throughout the toolflow means that the CAD toolswill not be able to optimize across module boundaries. If you are concerned about this you canremove the (*synthesize*) directive from your bluespec code, reverting to the Bluespec compiler’sdefault behavior of generating flattened Verilog. (additionally, you can instruct the CAD to ols toflatten the design before optimization)Figure 1 illustrates the 6.375 ASIC toolflow we will be using for the third lab. You should alreadybe familiar with the simulation and compilation paths f rom the first and second labs. The verilogused by the CAD tools will be generated by th e Bluespec compiler and all the coding you dofor this assignment should be in BSV. We will use Synopsys Design Compiler to synthesize thedesign. Synthesis is the process of tr ansforming an RTL model into a gate-level model. For this labassignment, Design Compiler will take th e RTL model of the SMIPSv2 processor as input alongwith a description of the standard cell library, and it w ill produce a Verilog netlist of standard cell6.375 Laboratory 2, Spring 2007 2TimingAreaVerilogSourceVCSBmarkStatsEncounter (FP) Design CompilerVirSimFloorPlanRTLSimVMHProgGateLevelNetlistTimingAreaLayoutEncouter GUIGateLevelNetlistVCSGateLevelSimPowerVCDEncounter (Power)Encounter (PAR)StdCellLibASMSourceCodeTestOutputsAssembler FlowExecute SimDesign VisionBluespec CompilerSourceBSVExecute SimFigure 1: 6.375 Toolflow for Lab 26.375 Laboratory 2, Spring 2007 3gates. Although the gate-level netlist is at a low-level functionally, it is still relatively abstract interms of the spatial placement and physical connectivity between the gates. We will use CadenceEncounter to place and route the design. Placement is the process by which each standard cellis positioned on the chip, while routing involves wiring the cells together using the various metallayers. Notice that you w ill b e receiving feedback on th e performance and area of your design afterboth synthesis and place+route - the results from synthesis are less realistic b ut are generatedrelatively rapidly, while the results from place+route are more realistic but require much moretime to generate. Place+route for your two-stage SMIPSv2 processor will take on the order of 15minutes, but for your projects it could take up to an hour. After place+route, we will generate andsimulate a final gate-level netlist using VCS. We can use this gate-level simulation as a final testfor correctness and to generate transition counts f or every net in the design. Encounter can takethese transition counts as input and correlate them with the capacitance values in the final layoutto produce dynamic power measurements.Each piece of the toolflow has its own build directory and its own makefile. Please consult thefollowing tutorials for more information on using the various parts of the toolflow. Note that thesetutorials are written for projects written explicitly in Verilog, but for this lab we will be coding inBluespec and generating Verilog code us ing the Bluespec compiler.• Tutorial 4: RTL-to-Gates Synthesis using Synopsys Design Compiler• Tutorial 5: Automatic Placement and Routing using Cadence EncounterGetting StartedAll of the 6.375 laboratory assignments should be completed on an Athena/Linux workstation.Please see the course website for more information on the computing resources available for 6.375students. Once you have logged into an Ath en a/Linux workstation you will need to setup the 6.375toolflow with the following command s .% add 6.375% source /mit/6.375/setup.cshYou will be using CVS to manage your 6.375 laboratory assignments. Please see Tutorial 2:
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