1February 20, 2007 http://csg.csail.mit.edu/6.375/ L06-1Bluespec-3:A non-pipelined processorArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 20, 2007L06-2http://csg.csail.mit.edu/6.375/OutlineFirst we will finish the last lecture Synchronous pipeline 802.11a results One-Element FIFO Non-pipelined processor with magic memory with decoupled, req-resp memory2February 20, 2007L06-3http://csg.csail.mit.edu/6.375/Pattern-matching: A convenient way to extract datasructure componentsThe &&& is a conjunction, and allows pattern-variables to come into scope from left to rightcase (m) matchestagged Invalid : return 0;tagged Valid .x : return x;endcaseif (m matches (Valid .x) &&& (x > 10))typedef union tagged {void Invalid;t Valid;} Maybe#(type t);February 20, 2007L06-4http://csg.csail.mit.edu/6.375/Synchronous pipelinexsReg1inQf1f2 f3sReg2 outQrule sync-pipeline (True);if (inQ.notEmpty())begin sReg1 <= Valid f1(inQ.first()); inQ.deq(); endelse sReg1 <= Invalid;case (sReg1) matchestagged Valid .sx1: sReg2 <= Valid f2(sx1);tagged Invalid: sReg2 <= Invalid;case (sReg2) matches tagged Valid .sx2: outQ.enq(f3(sx2));endrule3February 20, 2007L06-5http://csg.csail.mit.edu/6.375/Folded pipelinerule folded-pipeline (True);if (stage==1) begin sxIn= inQ.first(); inQ.deq(); endelse sxIn= sReg; sxOut = f(stage,sxIn);if (stage==n) outQ.enq(sxOut);else sReg <= sxOut;stage <= (stage==n)? 1 : stage+1;endrulexsReginQfoutQstageNeed type declarations for sxIn and sxOutFebruary 20, 2007L06-6http://csg.csail.mit.edu/6.375/802.11a Transmitter Synthesis results (Only the IFFT block is changing)1.0 MHz044.91Combinational (48 Bfly-4s)12 MHZ6.0 MHz3.0 MHz1.5 MHz1.0 MHz1.0 MHzMin. Freq Required482412060404ThroughputLatency(CLKs/sym)1.84SF(2 Bfly-4s)2.45SF(4 Bfly-4s)5.25Pipelined(48 Bfly-4s)1.523.693.97Area (mm2)SF (1 Bfly4)Super-Folded(8 Bfly-4s)Folded(16 Bfly-4s)IFFT DesignTSMC .18 micron; numbers reported are before place and route.4February 20, 2007L06-7http://csg.csail.mit.edu/6.375/Why are the areas so similarFolding should have given a 3x improvement in IFFT areaBUT a constant twiddle allows low-level optimization on a Bfly-4 block a 2.5x area reduction!February 20, 2007L06-8http://csg.csail.mit.edu/6.375/Parameterization: An n-stage synchronous pipeline Vector#(n, Reg#(t)) sReg <- replicateM(mkReg(Invalid));rule sync-pipeline (True);if (inQ.notEmpty())begin (sReg[1]) <= Valid f(1,inQ.first()); inq.deq(); endelse (sReg[1]) <= Invalid;for (Integer stage = 1; stage < n-1; stage = stage+1)case (sReg[stage]) matchestagged Valid .sx: (sReg[stage+1]) <= Valid f(stage+1,sx); tagged Invalid : (sReg[stage+1]) <= Invalid; endcasecase (sReg[n-1]) matches tagged Valid .sx: outQ.enq(f(n,sx)); endcaseendrulexsReg[1]inQf1fnsReg[n-1] outQn and stage are static parameters5February 20, 2007L06-9http://csg.csail.mit.edu/6.375/Syntax: Vector of RegistersRegister suppose x and y are both of type Reg. Thenx <= y means x._write(y._read())Vector of (say) Int x[i] means sel(x,i) x[i] = y[j] means x = update(x,i, sel(y,j))Vector of Registers x[i] <= y[j] does not work. The parser thinks it means (sel(x,i)._read)._write(sel(y,j)._read),which will not type check (x[i]) <= y[j] does work! February 20, 2007L06-10http://csg.csail.mit.edu/6.375/Action Value methodsValue method: Only reads the state; does not affect it e.g. fifo.first()Action method: Affects the state but does not return a value e.g. fifo.deq(), fifo.enq(x), fifo.clear()Action Value method: Returns a value but also affects the state e.g. fifo.pop() syntax: x <- fifo.pop()This use of <- is not to be confused with module instantiation reg <- mkRegU()6February 20, 2007L06-11http://csg.csail.mit.edu/6.375/module mkFIFO1 (FIFO#(t));Reg#(t) data <- mkRegU();Reg#(Bool) full <- mkReg(False);method Action enq(t x) if (!full);full <= True; data <= x;endmethodmethod Action deq() if (full);full <= False;endmethodmethod t first() if (full);return (data);endmethodmethod Action clear();full <= False;endmethodendmoduleOne-Element FIFOmethod ActionValue#(t) pop() if (full);full <= False; return (data);February 20, 2007 http://csg.csail.mit.edu/6.375/ L06-12A simple non-pipelined processorAnother example to illustrate simple rules and tagged unions (also to help you with Lab 2)7February 20, 2007L06-13http://csg.csail.mit.edu/6.375/Instruction settypedef enum {R0;R1;R2;…;R31} RName;An instruction set can be implemented using many different microarchitecturestypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName src; RName addr;} Store;} Instr deriving (Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 20, 2007L06-14http://csg.csail.mit.edu/6.375/Tagged Unions: Bit RepresentationAutomatically derived representation; can be customized by the user written pack and unpack functionstypedef union tagged {struct {RName dst; RName src1; RName src2;} Add;struct {RName cond; RName addr;} Bz;struct {RName dst; RName addr;} Load;struct {RName src; RName addr;} Store;} Instr deriving (Bits, Eq);00 dst src1 src201 cond addr10 dst addr11 src addr8February 20, 2007L06-15http://csg.csail.mit.edu/6.375/Non-pipelined Processorfetch & execute pciMem dMemrfCPUmodule mkCPU#(Mem iMem, Mem dMem)();Reg#(Iaddress) pc <- mkReg(0);RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1;rule fetch_Execute ...endmoduleAssumes “magic memory”, i.e. responds to a read request in the same cycle and updates the memory at the end of the cycle for a write requestFebruary 20, 2007L06-16http://csg.csail.mit.edu/6.375/Non-pipelined processor rulerule fetch_Execute (True);case (instr) matchestagged Add {dst:.rd,src1:.ra,src2:.rb}: beginrf.upd(rd, rf[ra]+rf[rb]);pc <= predIaendtagged Bz {cond:.rc,addr:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa;endtagged Load {dest:.rd,addr:.ra}: beginrf.upd(rd, dMem.read(rf[ra]));pc <= predIa;endtagged Store {value:.rv,addr:.ra}: begindMem.write(rf[ra],rf[rv]);pc <= predIa;endendcaseendrulemy syntaxrf[r] ≡ rf.sub(r)9February 20, 2007L06-17http://csg.csail.mit.edu/6.375/Syntax: RegFile vs VectorsA RegFile (register file) has a different type than a Vector of
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