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MIT 6 375 - Modeling Processors

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Slide 1Instruction setDeriving BitsTagged Unions: Bit RepresentationThe PlanNon-pipelined ProcessorNon-pipelined processor ruleRegister FileThe PlanTwo-stage Inelastic PipelineInstructions & TemplatesSlide 12Execute Action: Reads buReg and modifies state (rf,dMem,pc)Issues with buRegInelastic Pipeline first attemptExecutePipeline HazardsStall conditionSlide 19Inelastic Pipeline correctedBypassingGeneration of bypass register valueBypassing values to FetchNew fetchActionUpdated newItBypassingThe stall function for the Inelastic pipelineInelastic PipelinesModeling ProcessorsArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyFebruary 22, 2011 L07-1http://csg.csail.mit.edu/6.375Instruction settypedef enum {R0;R1;R2;…;R31} RName;An instruction set can be implemented using many different microarchitecturestypedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName valueR; RName addrR;} Store} Instr deriving(Bits, Eq);typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;February 22, 2011L07-2http://csg.csail.mit.edu/6.375Deriving BitsTo store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack)Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit representations of components)It is possible to customize the pack/unpack operations to any specific desired representationtypedef struct { … } Foo deriving (Bits);February 22, 2011L07-3http://csg.csail.mit.edu/6.375Tagged Unions: Bit Representation00 dst src1 src201 condR addrR10 dst addrR11 dst immtypedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);Automatically derived representation; can be customized by the user written pack and unpack functionsFebruary 22, 2011L07-4http://csg.csail.mit.edu/6.375The PlanNon-pipelined processorTwo-stage Inelastic pipelineTwo-stage Elastic pipeline – next lectureSome understanding of simple processor pipelines is needed to follow this lectureFebruary 22, 2011L07-5http://csg.csail.mit.edu/6.375Non-pipelined Processorfetch & execute pc iMem dMemrfCPUmodule mkCPU#(Mem iMem, Mem dMem)(); Reg#(Iaddress) pc <- mkReg(0); RegFile#(RName, Bit#(32)) rf <- mkRegFileFull();Instr instr = iMem.read(pc); Iaddress predIa = pc + 1; rule fetch_Execute ...endmoduleFebruary 22, 2011L07-6http://csg.csail.mit.edu/6.375Non-pipelined processor rulerule fetch_Execute (True); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: begin rf.upd(rd, rf[ra]+rf[rb]); pc <= predIa end tagged Bz {condR:.rc,addrR:.ra}: begin pc <= (rf[rc]==0) ? rf[ra] : predIa; end tagged Load {dest:.rd,addrR:.ra}: begin rf.upd(rd, dMem.read(rf[ra])); pc <= predIa; end tagged Store {valueR:.rv,addrR:.ra}: begin dMem.write(rf[ra],rf[rv]); pc <= predIa; end endcaseendrulemy syntaxrf[r]  rf.sub(r)Assume “magic memory”, i.e. responds to a read request in the same cycle and a write updates the memory at the end of the cyclePattern matchingFebruary 22, 2011L07-7http://csg.csail.mit.edu/6.375Register FileHow many read ports?TwoHow many write ports?OneConcurrency properties?Must be able to do two reads and a write concurrentlyThe values produced must be as if reads precede the write (if any)February 22, 2011L07-8http://csg.csail.mit.edu/6.375The PlanNon-pipelined processorTwo-stage Inelastic pipeline Two-stage Elastic pipelineFebruary 22, 2011L07-9http://csg.csail.mit.edu/6.375Two-stage InelasticPipelinefetch & decodeexecutebuRegtime t0 t1 t2 t3 t4 t5 t6 t7 . . . .FDstage FD1FD2FD3FD4FD5EXstage EX1EX2EX3EX4EX5Actions to be performed in parallel every cycle:Fetch Action: Decodes the instruction at the current pc and fetches operands from the register file and stores the result in buRegExecute Action: Performs the action specified in buReg and updates the processor state (pc, rf, dMem)pc rf dMemrule InelasticPipeline2(True);fetchAction; executeAction; endruleFebruary 22, 2011L07-10http://csg.csail.mit.edu/6.375Instructions & Templatestypedef union tagged { struct {RName dst; Value op1; Value op2} EAdd; struct {Value cond; Iaddress tAddr} EBz; struct {RName dst; Daddress addr} ELoad; struct {Value val; Daddress addr} EStore;} InstTemplate deriving(Eq, Bits);typedef union tagged { struct {RName dst; RName src1; RName src2} Add; struct {RName condR; RName addrR} Bz; struct {RName dst; RName addrR} Load; struct {RName valueR; RName addrR} Store;} Instr deriving(Bits, Eq);buReg contains instruction templates, i.e., decoded instructionsFebruary 22, 2011L07-11http://csg.csail.mit.edu/6.375Fetch & Decode ActionFills the buReg with a decoded instructionfunction InstrTemplate newIt(Instr instr); case (instr) matches tagged Add {dst:.rd,src1:.ra,src2:.rb}: return EAdd{dst:rd,op1:rf[ra],op2:rf[rb]}; tagged Bz {condR:.rc,addrR:.addr}: return EBz{cond:rf[rc],tAddr:rf[addr]}; tagged Load {dst:.rd,addrR:.addr}: return ELoad{dst:rd,addrR:rf[addr]}; tagged Store{valueR:.v,addrR:.addr}: return EStore{val:rf[v],addr:rf[addr]}; endcase endfunction buReg <= newIt(instr); February 22, 2011L07-12http://csg.csail.mit.edu/6.375Execute Action: Reads buReg and modifies state (rf,dMem,pc)case (buReg) matches tagged EAdd{dst:.rd,op1:.va,op2:.vb}: begin rf.upd(rd, va+vb); pc <= predIa; end tagged ELoad{dst:.rd,addr:.av}: begin rf.upd(rd, dMem.read(av)); pc <= predIa; end tagged EStore{val:.vv,addr:.av}: begin dMem.write(av, vv); pc <= predIa; end tagged EBz {cond:.cv,tAddr:.av}: if (cv != 0) then pc <= predIa; else begin pc <= av; Invalidate buReg endendcaseWhat does this mean?February 22, 2011L07-13http://csg.csail.mit.edu/6.375Issues with buRegfetch & decodeexecutebuRegbuReg may not always contain an instruction. Why?start cycleExecute stage may kill the fetched instructions because of


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MIT 6 375 - Modeling Processors

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