1February 6, 2009 http://csg.csail.mit.edu/6.375/ L02-1Verilog 1 - Fundamentals6.375 Complex Digital SystemsArvindFebruary 6, 2009FAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleFebruary 6, 2009 L02-2http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule2February 6, 2009 L02-3http://csg.csail.mit.edu/6.375/Originally designers used breadboards for prototypingNumber of Gatesin Design10102103104105106107Solderless BreadboardPrinted circuit board tangentsoft.net/elec/breadboard.htmlhome.cogeco.caNo symbolic execution or testingFebruary 6, 2009 L02-4http://csg.csail.mit.edu/6.375/HDLs enabled logic level simulation and testingGate Level DescriptionManualTestResultsSimulateNumber of Gatesin Design10102103104105106107HDL = Hardware Description Language3February 6, 2009 L02-5http://csg.csail.mit.edu/6.375/Designers began to use HDLs for higher level designGate LevelNumber of Gatesin Design10102103104105106107HDL models offered “precise” & executable specification but the translation between the levels remained manualBehavioralAlgorithmTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateManualFebruary 6, 2009 L02-6http://csg.csail.mit.edu/6.375/HDLs led to tools for automatic translationGate LevelNumber of Gatesin Design10102103104105106107HDLs: Verilog, VHDL…Tools: Spice, ModelSim, DesignCompiler, …BehavioralAlgorithmTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateManualLogic SynthesisAuto Place + Route4February 6, 2009 L02-7http://csg.csail.mit.edu/6.375/Raising the abstraction further …Gate LevelNumber of Gatesin Design10102103104105106107Bluespec and associated toolsGuarded AtomicActionsTestResultsSimulateRegisterTransfer LevelTestResultsSimulateTestResultsSimulateGAA CompilerLogic SynthesisAuto Place + RouteFebruary 6, 2009 L02-8http://csg.csail.mit.edu/6.375/The current situation BehavioralLevelRegisterTransfer LevelGate LevelLogic SynthesisBluespecStructural RTLVerilog, VHDL, SystemVerilogC, C++, SystemCBehavioral RTLVerilog, VHDL, SystemVerilogMATLABSimulators and other tools are available at all levels but not compilers from the behavioral level to RTL5February 6, 2009 L02-9http://csg.csail.mit.edu/6.375/Common misconceptionsThe only behavioural languages are C, C++RTL languages are necessarily lower-level than behavioral languages Yes- in the sense that C or SystemC is farther away from hardware No- in the sense that HDLs can incorporate the most advanced language ideas.Bluespec is a modern high-level language and at the same time can describe hardware to the same level of precision as RTLFebruary 6, 2009 L02-10http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6February 6, 2009 L02-11http://csg.csail.mit.edu/6.375/Bit-vector is the only data type in VerilogHigh impedance, floatingZUnknown logic valueXLogic one1Logic zero0MeaningValueAn X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality.A bit can take on one of four valuesFebruary 6, 2009 L02-12http://csg.csail.mit.edu/6.375/“wire” is used to denote a hardware netwire [15:0] instruction;wire [15:0] memory_req;wire [ 7:0] small_net;instructionmemory_reqinstructionsmall_net?Absolutely no type safety when connecting nets!7February 6, 2009 L02-13http://csg.csail.mit.edu/6.375/Bit literalsBinary literals 8’b0000_0000 8’b0xx0_1xx1Hexadecimal literals 32’h0a34_def1 16’haxxxDecimal literals 32’d424’b10_11Underscores are ignoredBase format(d,b,o,h)Decimal number representing size in bitsWe’ll learn how to actually assign literals to nets a little laterFebruary 6, 2009 L02-14http://csg.csail.mit.edu/6.375/Verilog FundamentalsHistory of hardware design languagesData typesStructural VerilogSimple behaviorsFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule8February 6, 2009 L02-15http://csg.csail.mit.edu/6.375/A Verilog module has a name and a port listadderABsumcoutmodule adder( A, B, cout, sum );input [3:0] A;input [3:0] B;output cout;output [3:0] sum;// HDL modeling of // adder functionalityendmoduleNote the semicolon at the end of the port list!Ports must have a direction (or be bidirectional) and a bitwidth4 44February 6, 2009 L02-16http://csg.csail.mit.edu/6.375/Traditional Verilog-1995 Syntaxmodule adder( A, B, cout, sum );input [3:0] A;input [3:0] B;output cout;output [3:0] sum;ANSI C Style Verilog-2001 Syntaxmodule adder( input [3:0] A,input [3:0] B,output cout,output [3:0] sum );Alternate syntaxadderABsumcout4 449February 6, 2009 L02-17http://csg.csail.mit.edu/6.375/A module can instantiate other modulesadderABScoutFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( ... );FA fa1( ... );FA fa2( ... );FA fa3( ... );endmodulemodule FA( input a, b, cinoutput cout, sum );// HDL modeling of 1 bit// full adder functionalityendmoduleFAbaccincoutFebruary 6, 2009 L02-18http://csg.csail.mit.edu/6.375/Connecting modulesadderABScoutFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmoduleCarry Chain10February 6, 2009 L02-19http://csg.csail.mit.edu/6.375/Alternative syntaxConnecting ports by ordered listFA fa0( A[0],
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