ESL: System Level Design Bluespec ESEPro: ESL Synthesis Extenstions for SystemCThe central ESL design problemAnother ESL design problemBluespec enables ESLRule Concurrent SemanticsBluespec Tools ArchitectureOutlineSlide 8A 2x2 switch, with statsThe first version of the SystemC code is easyCooperative parallelism modelThere could be some subtle mistakesHardware has additional “resource contention” constraintsSlide 14Slide 15Hardware typically has additional “resource contention” constraintsLimitations of SystemC/C++Other issues with SystemC/C++Literature on problems with threads (and the advantages of atomicity)2x2 switch: the meat of the ESEPro codeManaging changeSlide 22Interfaces: raising the level of abstraction (while preserving Rule semantics)Get and Put InterfacesSlide 25Interface transformers/transactorsSlide 27Nested interfacesSub-interfaces: using transformersClient/Server interfacesSlide 31Connecting Get and Put“Connectable” interface pairsmkConnectionSlide 35Rules and Levels of abstractionModule structureSimulation flowSynthesis flowSystem refinement Using ESEProMixing models: all combinationsStructure of TLM modules in demo (from OSCI_TLM/examples/example_3_2)TLM master and ESEPro slaveExample: ESEPro SoC model for synthesis (from ST/GreenSoCs “TAC” model)SoC Model: BehaviorSynthesis exampleSide-by-side simulation comparisonSoC Router: Magma Synthesis ResultsESL: System Level DesignBluespec ESEPro:ESL Synthesis Extenstions for SystemCRishiyur S. Nikhil CTO, Bluespec, Inc. (www.bluespec.com)6.375 Lecture 16 Delivered by ArvindMarch 16, 2007 (Only a subset of Nikhil’s slides are included)2Rishiyur Nikhil, Bluespec, Inc.Not avail. early;slower sim;HW-accurateexplore architectures(for speed, area. power)refineHW ImplementationimplementsSoftwareThe central ESL design problemAvail. early;very fast sim;not HW-accurate(timing, area)EarlysoftwareimplementsFirst HW model(s)HW/SW interface (e.g., register read/write)EarlymodelsRequired:uniform computational model(single paradigm), plus higher levelthan RTL, even for implementation3Rishiyur Nikhil, Bluespec, Inc.Another ESL design problemReuse (models and implementations)SoC 1 SoC 2 SoC nRequired:powerful parameterization andpowerful module interface semantics4Rishiyur Nikhil, Bluespec, Inc.Bluespec enables ESL•Rules and Rule-based Interfaces provide a uniform computational model suitable both for high-level system modeling as well as for HW implementation•Atomic Transaction semantics are very powerful for expressing complex concurrency– Formal and informal reasoning about correctness– Automatic synthesis of complex control logic to manage concurrency•Map naturally to HW (“state machines); synthesizable; no mental shifting of gears during refinement•Can be mixed with regular SystemC, TLM, and C++, for mixed-model and whole-system modeling•Enables Design-by-Refinement; Design-by-ContractBSV: Bluespec SystemVerilogESEPro: Bluspec’s ESL Synthesis Extensions to SystemC5Rishiyur Nikhil, Bluespec, Inc.Rule Concurrent Semantics•“Untimed” semantics:•“Timed”, or “Clock Scheduled” semantics (Bluespec scheduling technology)Forever: Execute any enabled ruleIn each clock:Execute a subset of enabled rules (in parallel, but consistent with untimed semantics)6Rishiyur Nikhil, Bluespec, Inc.Bluespec Tools ArchitectureSchedulingOptimizationRTL GenerationStatic CheckingPower OptimizationParsing ParsingBSV (SystemVerilog*)ESEPro (SystemC*)RTLgccsystemc.h,esl.h.exeCommonSynthesisEngineESEComp and BSCBluesimESE and ESEProRapid,Source-LevelSimulation andInteractiveDebug of BSVCycle-Accuratew/Verilog simCycle-Accuratew/Verilog simBlueview DebugUntimed& Timedsim simsynthesis7Rishiyur Nikhil, Bluespec, Inc.Outline•Limitations of SystemC in modeling SoCs•ESEPro’s Rule-based Interfaces•Model-to-implementation refinement with SystemC and ESEPro modules•Seamless interoperation of SystemC TLM and ESEPro modules•ESEPro-to-RTL synthesis•An example8Rishiyur Nikhil, Bluespec, Inc.Example illustrating why modeling hardware-accurate complex concurrency is difficult in standard SystemC (threads and events)9Rishiyur Nikhil, Bluespec, Inc.A 2x2 switch, with statsSpec:•Packets arrive on two input FIFOs, and must be switched to two output FIFOs•Certain “interesting packets” must be countedDetermineQueueDetermineQueue+1Countcertain packets10Rishiyur Nikhil, Bluespec, Inc.The first version of the SystemC code is easyDetermineQueueDetermineQueue+1Countcertain packetsvoid thread1 (){while (true) { Pkt x = in0->first(); in0->deq(); if (x.dest == 0) out0->enq (x); else out1->enq (x); if (count(x)) c++;}}void thread2 (){while (true) { Pkt x = in1->first(); in1->deq(); if (x.dest == 0) out0->enq (x); else out1->enq (x); if (count(x)) c++;}}first(), deq() block if input fifo is empty;enq() blocks if output fifo is full.It all works fine because of “cooperative parallelism”11Rishiyur Nikhil, Bluespec, Inc.Cooperative parallelism model •The two increments to the counter do not need to be protected with “locks” because of SystemC’s definition of parallelism as cooperative, i.e.,•Threads only switch at “wait()” statements•Threads do not interleave•But real hardware has real parallelism!•Gap between model and implementation•Further, cooperative multithreading also makes it hard to simulate models in parallel (e.g., on a modern multi-core or SMP machine)This code would have problems with preemptive parallelism12Rishiyur Nikhil, Bluespec, Inc.There could be some subtle mistakesDetermineQueueDetermineQueue+1Countcertain packetsvoid thread1 (){while (true) { int tmp = c ; Pkt x = in0->first(); in0->deq(); if (x.dest == 0) out0->enq (x); else out1->enq (x); if (count(x)) c = tmp + 1 ;}}void thread2 (){while (true) { int tmp = c ; Pkt x = in1->first(); in1->deq(); if (x.dest == 0) out0->enq (x); else out1->enq (x); if (count(x)) c = tmp + 1 ;}}If the threads interleave due to blockingof first(), deq(), enq(), c will beincorrectly updated (non-atomically)Cooperative parallelism Atomicity13Rishiyur Nikhil, Bluespec, Inc.Hardware has additional “resource contention” constraints•Each output fifo can be enq’d by only one process at a time (in the same clock)•Need arbitration if both processes want to enq() on the same fifo simultaneously•SystemC’s cooperative multitasking makes it easy to ignore this, but much
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