FPGA Implementation of a Three-Stage SMIPSv2Processor6.375 Laboratory 3Kyle FritzJeff SimpsonMarch 13, 2009DeliverablesThe code for this laboratory assignment are available in CVS. A default checkout can beperformed as follows:> cvs checkout 2009s/students/je18337/lab3This will check out the most recently committed version of the software, which will includethe UART controls (Question #5), the breakp oint handling (Question #2), the branch pre-dictor (Question #4) and the RWire refinements (Question #3). Individual tagged releasesare available:refinement : This release contains refinements to improve IPC, including a bypass registerfile. It also contains the previous releases: the serial UART, Breakp oint handling, andbranch prediction.serialbreakpoint bpred sim : This release contains the serial UART control, breakpointhandling, and branch prediction. This release will pass simulations but the breakpointswill not function on the FPGA.serial breakpoint bpred : This release contains the Serial UART control, breakpointhandling, and branch predictor. The breakpoints will function on the FPGA in thisrelease but will not pass simulation tests.1serial breakpoint : This release contains serial UART control and breakpoint handling.serialv1 : This release contains only the serial UART control.To switch to a specific release version, use the following command:> cvs update -r [releasename] 2009s/students/je18337/lab3/src(note that only the src directory will differ from version to version, generally)Critical Thinking Questi onsQuestion 1: Evaluate Your Baseline Pro cessorPost-synthesis resource consumption of the register file flattenedLogic Register RAM MultiplierElem. Util. Elem. Util. Elem. Util. Elem. Util.1431 24.00% 1024 33.6% 0 0% 0 0%Post-synthesis resource consumption of the register file unflattenedLogic Register RAM MultiplierElem. Util. Elem. Util. Elem. Util. Elem. Util.1424 24.10% 1024 34.2% 0 0% 0 0%Post-synthesis resource consumption of the data path, excluding register file (* synthesis * )of mkProc unflattenedLogic Register RAM MultiplierElem. Util. Elem. Util. Elem. Util. Elem. Util.3567 60.40% 1535 51.3% 0 0% 0 0%Post-synthesis resource consumption of the processor flattened2Logic Register RAM MultiplierElem. Util. Elem. Util. Elem. Util. Elem. Util.5969 100.0% 3049 100.0% 4 100.0% 4 100.0%Post-synthesis resource consumption of the processor unflattenedLogic Register RAM MultiplierElem. Util. Elem. Util. Elem. Util. Elem. Util.5910 100.0% 2993 100.0% 4 100.0% 4 100.0%Post-place&route r esource consumption of the processor unflattenedLogic Elements Register Elements RAM Bits6060 2869 108544The post-place+route results are worse than the post-synthesis results because the synthesisstep doesn’t have any knowledge of the actual positions of elements on the FPGA. Theplace+route step is limited by the physical hardware and, as such, must make use of moreelements to achieve a correct result.After running through the toolflow, our processor immediately met the 50 MHz clock ratewithout any extra debugging.Question 2: BreakpointsTo enable a breakpoint in the execution of instructions of our processor, one must indicate,in the NIOS code, the types of instructions at which to break. After debating whether ornot to sp ecify breakpoints by PC, we decided our system would be more flexible if we couldspecify breakpoints for all instructions that matched a certain pattern. We were worriedthat setting breakpoints by PC would require significant inspection of tests’ a ssembly todetermine where to set a breakpoint. Our approach makes it easy; you just break at anyinstruction that matches a specific pattern. For example, we can set a breakpoint at anyADDU instruction. Alternatively, we can set a breakpoint at any instruction with r1 a s therd. We can also mix these cases together and only set a breakpoint at any ADDU instructionthat writes to register r1.To set a breakpoint, one must edit the C code for the NIOS processor. Two int variables3must be set, breakpointIns truction and breakpointMask. The breakpointInstruction variablecontains the bits of the instructions at which we want to break; each fetched instructionis compared with the value of breakpointInstruction. The breakpointMask variable is a bitvector that indicates which bits of the instruction are to be ignored during the comparison.For example, if you wanted to stop at all ADDU instructions use the following values:int breakpointInstruction = 0b 000000 00000 00000 00000 00000 100001;int breakpointMask = 0b 000000 11111 11111 11111 00000 000000;If you wanted to stop at all instructions that have r1 in its rd location:int breakpointInstruction = 0b 000000 00000 00000 00001 00000 000000;int breakpointMask = 0b 111111 11111 11111 00000 11111 111111;Finally, if you wanted to stop at all ADDU instructions t hat write to r1:int breakpointInstruction = 0b 000000 00000 00000 00001 00000 100001;int breakpointMask = 0b 000000 11111 11111 00000 00000 000000;The NIOS processor copies these values to registers on the SMIPS via CBus before executionbegins. As the SMIPS processor runs, NIOS will watch for a signal on the CBus that indicatesa breakpoint has been encountered. NIOS can then print any values from CBus to the serialconnection for debugging purposes. Our NIOS will also blink an LED when the breakpointis encountered. Aft er printing, NIOS sends a signal over CBus to clear the breakpoint.The SMIPS processor has a few rules and functions to determine if the currently fetchedinstruction matches the specified pattern a nd to hold executing that instruction.The inBreakpoint() function returns True if the processor should hold execution and Falseotherwise. The default result is False. It first checks whether the first instruction bits inthe instRespQ match the pattern via the compareInstructionBitsForBreakpoint() function;if they do, it sets the result to True. It then checks whether the NIOS has cleared thebreakpoint; if it has, then it resets the result to False. Finally, it returns the result.The compare InstructionBitsForBreakpoint() function returns True if the given instructionbits match the pattern, ignoring any bits set in the mask and False otherwise. It firstors the breakpointMask with the current instruction bits. It then compares tha t with thebreakpointInstruction; a match indicates that the current instruction fits the pattern andwe should break.The exec rule uses ! i nBreakpoint() in its g ua rd. It should not fire if we
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