Slide 1Do we need more chips (ASICs)? ASIC=Application Specific ICContent distribution and customer serviceUbiquitous, behind-the-scenes computingWhat’s required?Current Cellphone ArchitectureChip design has become too risky a businessDesigner’s DilemmaOne prevailing viewpoint: A sea of general purpose processorsAnother popular “platform” vision: Field-Programmable Gate ArraysFuture could be different if we became 10X more productive in designLet’s take a look at the current CMOS technology...FET = Field-Effect Transistor A four terminal device (gate, source, drain, bulk)Simplified FET ModelNAND GateNAND Gate LayoutDesign RulesExponential growth: Moore’s LawIBM Power 5Hardware Design Abstraction LevelsTools play a crucial role in our ability to design economicallyASIC Design StylesCustom and Semi-CustomStandard Cell ASICs aka Cell-Based ICs (CBICs)Standard Cell DesignStandard Cell Design ExamplesGate ArraysGate Array PersonalizationGate Array Pros and ConsField-Programmable Gate ArraysXilinx Configurable Logic Block6.375 ASIC/FPGA Design Flow6.375 Course Philosophy6.375 Objectives By end of term, you should be able to:6.375 Prerequisites6.375 Structure6.375 Project (see course web page)6.375 Grade Breakdown6.375 Collaboration PolicyFebruary 8, 2006 http://csg.csail.mit.edu/6.375/ L01-16.375 Complex Digital SystemSpring 2006Lecturer: Arvind TAs: Chris Batten & Mike PellauerAssistant: Sally LeeFebruary 8, 2006 L01-2http://csg.csail.mit.edu/6.375/Do we need more chips (ASICs)?ASIC=Application Specific ICSome exciting possibilities based on research @ CSAILFebruary 8, 2006 L01-3http://csg.csail.mit.edu/6.375/Content distribution andcustomer serviceInteractive, lifelike avatars as actors, news anchors, and customer service representatives Source: Computer Science and Artificial Intelligence Laboratory at MIT (CSAIL)February 8, 2006 L01-4http://csg.csail.mit.edu/6.375/Ubiquitous, behind-the-scenes computingComputer interfaces woven tightly into the environment Source: Computer Science and Artificial Intelligence Laboratory at MIT (CSAIL)February 8, 2006 L01-5http://csg.csail.mit.edu/6.375/Source: http://www.intel.com/technology/silicon/mooreslaw/index.htmWhat’s required?ICs with dramatically higher performance, optimized for applicationsand at a size and power to deliver mobility; cost to address mass consumer marketsFebruary 8, 2006 L01-6http://csg.csail.mit.edu/6.375/Current Cellphone ArchitectureComms. ProcessingApplication ProcessingWLAN RFWLAN RFWLAN RFWCDMA/GSM RFTwo chips, each with an ARM general-purpose processor (GPP) and a DSPTI OMAP 2420COMPLEXFebruary 8, 2006 L01-7http://csg.csail.mit.edu/6.375/Chip design has become too risky a business Ever increasing size and complexityMicroprocessors: 100M gates 1000M gatesASICs: 5M to 10M gates 50M to 100M gatesEver increasing costs and design team sizes> $10M for a 10M gate ASIC> $1M per re-spin in case of an error (does not include the redesign costs, which can be substantial)18 months to design but only an eight-month selling opportunity in the market Fewer new chip-starts every year Looking for alternatives, e.g., FPGA’sFebruary 8, 2006 L01-8http://csg.csail.mit.edu/6.375/Designer’s DilemmaSub-optimal implementations!Designer must take shortcutsConservative designNo time for explorationEducated guess & codeGates are free mentalityConstants10-30 person design team size 18 month design scheduleDesign flow -- unchanged for 10+ years!ASIC Complexity2000: 1M+ logic gates2005: 10M+ logic gates2010: 100M+ logic gatesLPM PipelineArea(gates)Speed(ns)Memory Util (%)Static8,898 3.60 63.5Linear15,9104.70 99.9Circular8,170 3.67 99.9Static (2)2,391 3.32 63.5What happens when a designer must implement a 1M gate block?Alternatives?[ICCAD’04]LPM Pipeline example:Which is best?February 8, 2006 L01-9http://csg.csail.mit.edu/6.375/One prevailing viewpoint:A sea of general purpose processorsAdvantagesEasier to scale hardwaredesign as complexityis contained within processorsEasy to program and debug complex applicationsIBM/Sony Cell Processor Do we really know how to program these?Disadvantages (as compared to an ASIC)Power ~100-1000X worse Performance up to ~100X worseArea up to ~10-100X greaterFebruary 8, 2006 L01-10http://csg.csail.mit.edu/6.375/Another popular “platform” vision: Field-Programmable Gate ArraysAdvantagesDramatically reduce the cost of errorsRemove the reticle costs from each designDisadvantages (as compared to an ASIC)[Kuon & Rose, FPGA2006]Switching power around ~12X worsePerformance up 3-4X worseArea 20-40X greaterStill requires tremendous design effort at RTL levelFebruary 8, 2006 L01-11http://csg.csail.mit.edu/6.375/Future could be different if we became 10X more productive in designThis course is about new ways expressing behavior to reduce design complexityDecentralize complexity: Rule-based specifications (Guarded Atomic Actions)Let us think about one rule at a timeFormalize composition: Modules with guarded interfacesAutomatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodologyRetain resilience to changes in design or layout, e.g. compute latency ’sPromote regularity of layout at macro levelFebruary 8, 2006 L01-12http://csg.csail.mit.edu/6.375/Let’s take a look at the current CMOS technology...February 8, 2006 L01-13http://csg.csail.mit.edu/6.375/FET = Field-Effect TransistorA four terminal device (gate, source, drain, bulk)EhInversion: A vertical field creates a channel between the source and drain.Conduction: If a channel exists, a horizontal field causes a drift current from the drain to the source.EvSource diffusionDrain diffusiongatebulkSurface of waferReverse side of waferinversionhappens hereFebruary 8, 2006 L01-14http://csg.csail.mit.edu/6.375/Simplified FET ModelGPFET connects S and D when G=“low”=0VGNFET connects D and S when G=“high”=VDDSDSDGPFET only good at pulling upGNFET only good at pulling downSupply Voltage = VDDGround = GND = 0VBinary logic values represented by voltages:“High” = Supply Voltage, “Low” = Ground VoltageFebruary 8, 2006 L01-15http://csg.csail.mit.edu/6.375/NAND GateAB(A.B) When both A and B are high, output is low When either A or B is low, output is highBA(A.B)February 8, 2006 L01-16http://csg.csail.mit.edu/6.375/NAND Gate LayoutAB(A.B)Series NMOS TransistorsParallel PMOS
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