Project DescriptionIntroduction to Re-Order Buffer and Superscalar ProcessorOut-of-Ordering ExecutionRe-Order Buffer with Unified Physical Register FileHigh-level Processor DesignLife Cycles of Instructions in Re-order BufferALU instructionsBranch/Jump instructionsMemory instructionsBranch Unit, Branch Resolution and SnapshotsMemory Address UnitPipeline StagesData Dependency LoopArchitectural Summary of High-level DesignMicroarchitecture and Bluespec ImplementationProcessor ModuleRe-ordering ModuleLeaf ModulesFree ListRenaming TablePhysical Register FileALU ROBMemory ROBShifted Priority DecoderObtaining High Rule ConcurrencyCalling RelationshipRead-Write PatternRead-Write Pattern in ROBRead-Write Pattern in the Physical Register FileMultiple Write ProblemMethodologiesStructural Coding Style vs. EHRField SplittingCritical Path ConsiderationSafe Non-Coherent EHR IndexUnsafe Non-Coherent EHR IndexResultsRemained ConflictionCritical PathDesign Exploration and EvaluationExploration DimensionThe Size of ROBAdjusting Pipeline StagesEvaluation ResultsHardware costApplication PerformanceFinal Physical OptimizationMethodologyThe Journey of Physical OptimizationEHR Simplification FallacyOptimizing Shifted Priority DecoderResult of Physical OptimizationConclusion and Future WorkAppendix – Work on Bluespec / Bluespec CompilerNo automatic multiplexing when the called module is synthesized separatelySymptomSolutionUnusable constant in static elaboration stageSymptomSolutionRun-time system uses up huge memorySymptomSolutionNeeding explicit hardware decompositionSymptomSolutionParameterization and ProvisosSymptomSolutionAssignment on VectorSymptomSolutionMassachusetts Institute of Technology 6.375 Complex Digital System 2007 Spring Re-Order Buffer for Superscalar SMIPSv2 Processor Final Project Group IV Wei-Yin Chen [email protected] Myong Hyon Cho [email protected] In this project, we designed and implemented an out-of-ordering superscalar SMIPSv2 processor. The key of this project is designing a re-order buffer which controls a lot of information to tell whether each instruction is ready to be executed, committed, or discarded. Also, we used multiple number of operation units for the processor, including an ALU unit, a branch resolution unit, and an address calculation unit for memory instructions, to improve the performance even further. To deal with various situations, this processor has to be far more complex than in-order processors. Furthermore, jumps/branches and memory loads/stores were especially difficult and needed to be considered very carefully. Using Bluespec was another key point for this project. It enabled for us to develop the processor in a high-level point of view and guarantee correctness by construct, but at the same time, we needed to understand Bluespec well to make sure it produces a hardware design that we wanted to implement. Specifically, attaining high rule concurrency was not easy, and keeping the critical path short was also far from trivial. We faced a number of challenges, but we ended up with a working processor that can speculatively execute all ALU instructions and memory address calculation out-of-order with the optimal rule concurrency possible with a single write-port register file. The re-ordering superscalar machine has as high performance as SMIPSv2 processor in Lab3 which solved the data dependency problem in another way. After exploiting wide pipeline superscalar architecture, it will excel the processor in Lab3.Index 1. Project Description ................................................................................................................................ 5 2. Introduction to Re-Order Buffer and Superscalar Processor .............................................. 5 2.1. Out-of-Ordering Execution ................................................................................................. 5 2.2. Re-Order Buffer with Unified Physical Register File ............................................... 6 3. High-level Processor Design .............................................................................................................. 7 3.1. Life Cycles of Instructions in Re-order Buffer ............................................................ 7 3.1.1. ALU instructions ..................................................................................................... 7 3.1.2. Branch/Jump instructions .................................................................................. 8 3.1.3. Memory instructions ............................................................................................. 8 3.2. Branch Unit, Branch Resolution and Snapshots ........................................................ 8 3.3. Memory Address Unit ........................................................................................................... 9 3.4. Pipeline Stages ......................................................................................................................... 9 3.5. Data Dependency Loop ...................................................................................................... 11 3.6. Architectural Summary of High-level Design ........................................................... 11 4. Microarchitecture and Bluespec Implementation .................................................................. 12 4.1. Processor Module ................................................................................................................. 12 4.2. Re-ordering Module ............................................................................................................ 15 4.3. Leaf Modules .......................................................................................................................... 16 4.3.1. Free List .................................................................................................................... 16 4.3.2. Renaming Table..................................................................................................... 17 4.3.3. Physical Register File .......................................................................................... 17 4.3.4. ALU ROB ................................................................................................................... 18 4.3.5. Memory ROB
View Full Document
Unlocking...