Verilog 1 - Fundamentals6.375 Complex Digital SystemsChristopher BattenFebruary 9, 2006FAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 26.375 Course StructureFirst half of term before spring break• Lectures MWF, 2:30pm to 4:00pm in 32-124• Four lab assignments– Lab #1 : Verilog RTL for 2-stage SMIPSv2 processor– Lab #2 : Push SMIPSv2 processor through to layout– Lab #3 : Bluespec RTL for 4-stage SMIPSv2 processor– Lab #4 : Bluespec RTL for non-blocking cache• Project preparation– Form project team (2-3 students)– Prepare preliminary project proposal• Closed-book 90 minute quiz (March 24)6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 36.375 Course StructureSecond half of term after spring break• Weekly project meetings with instructors• Weekly milestones with 1-2 page report• Final project presentations last week of classes• Final project report – Approximately 15-20 pages– Due May 17 (no extensions!)6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 46.375 Course StructureSemester long design project• Two standard projects with fixed interfaces, infrastructure, and testbenches– SMIPS microprocessor• High performance (e.g. multicore, ooo superscalar)• Low power (e.g. fetch throttling, instruction fusion)• Minimal area (e.g. multiplexed byte-wide datapath)– SMIPS memory system• Cache-coherent multicore• DRAM memory access scheduler• Hardware prefetching6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 56.375 Course StructureSemester long design project• Custom or non-standard projects– Submit 2 page proposal by March 17 for approval– C/C++/Java reference implementation by March 22– Ex: MP3 player, graphics pipeline, network processor802.11a Encoder, 20056.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 66.375 Course StructureGrade breakdownFour labs 30%Quiz 20%Project milestones 25%Final project report 25%6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 76.375 Course StructureOpportunities for exceptional projects• Possibility of fabrication– Implement in 180nm technology– Summer and fall commitment– Significant work is required to prepare final project for fabrication• Possibility of targeting FPGA– Various development boards are available– Requires different toolchain6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 8Verilog Fundamentals• History of hardware design languages• Data types• Structural Verilog• Functional Verilog– Gate level– Register transfer level– High-level behavioralFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 9Originally designers used manual translation + bread boards for verificationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsBreadBoardNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 10Hardware design languages enabled logic level simulation and verificationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 11Designers began to use HDLs for higher level verification and design explorationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsSimulateTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 12HDL behavioral models act as a precise and executable specificationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualManualTestResultsSimulateTestResultsSimulateTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 13Once designs were written in HDLs tools could be used for automatic translationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualManualAuto Place + RouteTestResultsSimulateTestResultsSimulateTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 14Once designs were written in HDLs tools could be used for automatic translationBehavioralAlgorithmRegisterTransfer LevelGate LevelManualLogic SynthesisAuto Place + RouteTestResultsSimulateTestResultsSimulateTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 15Guarded atomic actions can help us to efficiently raise the abstraction level BehavioralAlgorithmRegisterTransfer LevelGate LevelLogic SynthesisTestResultsSimulateTestResultsSimulateTestResultsSimulateGuarded Atomic ActionsAction CompilerManualTestResultsSimulateNumber of Gatesin Design101021031041051061076.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 16Various hardware design languages are availableAdds strong type checking; separates interface from implementationSystemVerilogUses guarded atomic actions; advanced static elaboration and type system; separates interface from implementationBluespecADA-like verbose syntax; extensible types; DoD mandate; separates interface from implementation; operator overloadingVHDLSeveral small changes to avoid common mistakes; static elaborationVerilog-2001C-like concise syntax; only bit vector data types; very-low levelVerilog-19956.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 17Verilog Fundamentals• History of hardware design languages• Data types• Structural Verilog• Functional Verilog– Gate level– Register transfer level– High-level behavioralFAFA FA FAmodule adder( input [3:0] A, B,output cout,output [3:0] S );wire c0, c1, c2;FA fa0( A[0], B[0], 1’b0, c0, S[0] );FA fa1( A[1], B[1], c0, c1, S[1] );FA fa2( A[2], B[2], c1, c2, S[2] );FA fa3( A[3], B[3], c2, cout, S[3] );endmodule6.375 Spring 2006 • L02 Verilog 1 - Fundamentals • 18Primary Verilog data type is a bit-vector where bits can take on one of four valuesHigh impedance, floatingZUnknown logic valueXLogic one1Logic zero0MeaningValueAn X bit might be a 0,
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