Verilog 2 Design Examples 6 375 Complex Digital Systems Arvind February 9 2009 February 9 2009 http csg csail mit edu 6 375 L03 1 Verilog can be used at several levels High Level Behavioral A common approach is to use C C for initial behavioral modeling and for building test rigs Register Transfer Level automatic tools to synthesize a low level gate level model Gate Level February 9 2009 http csg csail mit edu 6 375 L03 2 1 Writing synthesizable Verilog Combinational logic Use continuous assignments assign assign C in B out 1 Use always blocks with blocking assignments always blocks allow always begin out 2 d0 if in1 1 out 2 d1 else if in2 1 out 2 d2 end more expressive control structures though not all will synthesize default Every variable should have a default value to avoid inadvertent introduction of latches Do not assign the same variable from more than one always block ill defined semantics February 9 2009 http csg csail mit edu 6 375 L03 3 Writing synthesizable Verilog Sequential logic Use always posedge clk and nonblocking assignments always posedge clk C out C in Use only positive edge triggered flip flops for state Do not assign the same variable from more than one always block ill defined semantics Do not mix blocking and non blocking assignments Only leaf modules should have functionality use higher level modules only for wiring together sub modules February 9 2009 http csg csail mit edu 6 375 L03 4 2 An example wire A in B in C in reg A out B out C out always posedge clk begin A out A in B out A out 1 C out B out 1 end A B 1 C 1 The order of non blocking assignments does not matter The effect of non blocking assignments is not visible until the end of the simulation tick February 9 2009 L03 5 http csg csail mit edu 6 375 Another way wire A in B in C in reg A out B out C out always posedge clk begin A out A in B out B in C out C in end A B 1 C 1 B in and C in are evaluated as needed assign B in A out 1 assign C in B out 1 February 9 2009 http csg csail mit edu 6 375 L03 6 3 An example Some wrong solutions wire A in B in C in reg A out B out C out A 1 always posedge clk begin A out A in B out B in C out C in assign B in A out 1 assign C in B out 1 end February 9 2009 B C 1 Syntactically illegal L03 7 http csg csail mit edu 6 375 Another style multiple always blocks wire A in B in C in reg A out B out C out always posedge clk A out A in A B 1 C 1 assign B in A out 1 always posedge clk B out B in assign C in B out 1 always posedge clk C out C in February 9 2009 Does it have the same functionality Yes But why Need to understand something about Verilog execution semantics http csg csail mit edu 6 375 L03 8 4 Yet another style blocking assignments wire A in B in C in reg A out B out C out always begin 1 A out 3 B out 5 C out end A 1 posedge clk A in B in C in 2 assign B in A out 1 4 assign C in B out 1 B 1 Does it have the same functionality Not even close 1 February 9 2009 C 1 http csg csail mit edu 6 375 L03 9 Verilog execution semantics Driven by simulation Explained using event queues February 9 2009 http csg csail mit edu 6 375 L03 10 5 Execution semantics of Verilog 1 Active Event Queue wire A in B in C in reg A out B out C out always posedge clk A out A in A assign B in A out 1 1 always posedge clk B out B in B assign C in B out 1 2 always posedge clk C out C in C February 9 2009 C B A On clock edge all those events which are sensitive to the clock are added to the active event queue in any order L03 11 http csg csail mit edu 6 375 Execution semantics of Verilog 2 Active Event Queue wire A in B in C in reg A out B out C out always posedge clk A out A in A assign B in A out 1 1 always posedge clk B out B in B assign C in B out 1 2 always posedge clk C out C in C February 9 2009 C 1 C B B A A evaluates and as a consequence 1 is added to the event queue http csg csail mit edu 6 375 L03 12 6 Execution semantics of Verilog 3 wire A in B in C in reg A out B out C out Active Event Queue always posedge clk A out A in A assign B in A out 1 1 always posedge clk B out B in B assign C in B out 1 2 always posedge clk C out C in C February 9 2009 1 C 2 1 C B Event B evaluates queue is and emptied as a consequence before we go2 to is added next to the clock event cycle queue http csg csail mit edu 6 375 L03 13 Non blocking assignment Within a simulation tick all RHS variables are read first and all the LHS variables are updated together at the end of the tick Consequently two event queues have to be maintained one keeps the computations to be performed while the other keeps the variables to be updated February 9 2009 http csg csail mit edu 6 375 L03 14 7 Non blocking assignments require two event queues Active Event Queue wire A in B in C in reg A out B out C out always posedge clk A out A in A assign B in A out 1 1 always posedge clk B out B in B assign C in B out 1 2 always posedge clk C out C in C February 9 2009 2 1 C B A R R R Non Blocking Queue C B A L L L Variables in RHS of always blocks are not updated until all inputs e g LHS dependencies are evaluated L03 15 http csg csail mit edu 6 375 Blocking assignments have a sequential language like semantics wire A in B in C in reg A out B out C out 1 2 3 always begin A out B out C out end 4 5 assign B in A out 1 assign C in B out 1 A posedge clk B 1 C 1 A in B in C in 1 1 Sequence of events 1 2 3 4 5 I am not 100 sure It …
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