SMIPS Processor Specification 6 375 Complex Digital Systems March 21 2006 SMIPS is the version of the MIPS instruction set architecture ISA we ll be using for the processors we implement in 6 884 SMIPS stands for Simple MIPS since it is actually a subset of the full MIPS ISA The MIPS architecture was one of the first commercial RISC reduced instruction set computer processors and grew out of the earlier MIPS research project at Stanford University MIPS stood for Microprocessor without Interlocking Pipeline Stages and the goal was to simplify the machine pipeline by requiring the compiler to schedule around pipeline hazards including a branch delay slot and a load delay slot Today MIPS CPUs are used in a wide range of devices Casio builds handheld PDAs using MIPS CPUs Sony uses two MIPS CPUs in the Playstation 2 many Cisco internet routers contain MIPS CPUs and Silicon Graphics makes Origin supercomputers containing up to 512 MIPS processors sharing a common memory MIPS implementations probably span the widest range for any commercial ISA from simple single issue in order pipelines to quad issue out of order superscalar processors There are several variants of the MIPS ISA The ISA has evolved from the original 32 bit MIPS I architecture used in the MIPS R2000 processor which appeared in 1986 The MIPS II architecture added a few more instructions while retaining a 32 bit address space The MIPS II architecture also added hardware interlocks for the load delay slot In practice compilers couldn t fill enough of the load delay slots with useful work and the NOPs in the load delay slots wasted instruction cache space Removing the branch delay slots might also have been a good idea but would have required a second set of branch instruction encodings to remain backwards compatible The MIPSIII architecture debuted with the MIPS R4000 processor and this extended the address space to 64 bits while leaving the original 32 bit architecture as a proper subset The MIPS IV architecture was developed by Silicon Graphics to add many enhancements for floating point computations and appeared first in the MIPS R8000 and later in the MIPS R10000 Over the course of time the MIPS architecture has been widely extended occasionally in non compatible ways by different processor implementors MIPS Technologies who now own the architecture are trying to rationalize the architecture into two broad groupings MIPS32 is the 32 bit address space version MIPS64 is the 64 bit address space version There is also MIPS16 which is a compact encoding of MIPS32 that only uses 16 bits for each instruction You can find a complete description of the MIPS instruction set at the MIPS Technologies web site 2 or in the book by Kane and Heinrich 3 The book by Sweetman also explains MIPS programming 4 Another source of MIPS details and implementation ideas is Computer Organization and Design The Hardware Software Interface 1 The SMIPS CPU implements a subset of the MIPS32 ISA It does not include floating point instructions trap instructions misaligned load stores branch and link instructions or branch likely instructions There are three SMIPS variants which are discussed in more detail at the end of this document SMIPSv1 has only five instructions and it is mainly used as a toy ISA for instructional SMIPSv2 includes the basic integer memory and control instructions It excludes multiply instructions divide instructions byte halfword loads stores and instructions which cause arithmetic overflows Neither SMIPSv1 or SMIPSv2 support exceptions interrupts or most of the system coprocessor SMIPSv3 is the full SMIPS ISA and includes everything described in this document SMIPS Specification Spring 2006 1 2 Basic Architecture Figure 1 shows the programmer visible state in the CPU There are 31 general purpose 32 bit registers r1 r31 Register r0 is hardwired to the constant 0 There are three special registers defined in the architecture two registers hi and lo are used to hold the results of integer multiplies and divides and the program counter pc holds the address of the instruction to be executed next These special registers are used or modified implicitly by certain instructions SMIPS differs significantly from the MIPS32 ISA in one very important respect SMIPS does not have a programmer visible branch delay slot Although this slightly complicates the control logic required in simple SMIPS pipelines it greatly simplifies the design of more sophisticated out oforder and superscalar processors As in MIPS32 Loads are fully interlocked and thus there is no programmer visible load delay slot Multiply instructions perform 32 bit 32 bit 64 bit signed or unsigned integer multiplies placing the result in the hi and lo registers Divide instructions perform a 32 bit 32 bit signed or unsigned divide returning both a 32 bit integer quotient and a 32 bit remainder Integer multiplies and divides can proceed in parallel with other instructions provided the hi and lo registers are not read The SMIPS CPU has two operating modes user mode and kernel mode The current operating mode is stored in the KUC bit in the system coprocessor COP0 status register The CPU normally operates in user mode until an exception forces a switch into kernel mode The CPU will then normally execute an exception handler in kernel mode before executing a Return From Exception ERET instruction to return to user mode General Purpose Registers Program Counter 31 0 31 0 r31 pc r30 Multiply Divide Registers 31 0 hi r1 lo r0 Figure 1 SMIPS CPU registers 3 SMIPS Specification Spring 2006 2 System Control Coprocessor CP0 The SMIPS system control coprocessor contains a number of registers used for exception handling communication with a test rig and the counter timer These registers are read and written using the MIPS standard MFC0 and MTC0 instructions respectively User mode can access the system control coprocessor only if the cu 0 bit is set in the status register Kernel mode can always access CP0 regardless of the setting of the cu 0 bit CP0 control registers are listed in Table 1 Number 0 7 8 9 10 11 12 13 14 15 19 20 21 22 31 Register badvaddr count compare status cause epc fromhost tohost Description unused Bad virtual address Counter timer register unused Timer compare register Status register Cause of last exception Exception program counter unused Test input register Test output register unused Table 1 CP0 control registers 2 1 Test Communication Registers 31 8 0 24 31 0 fromhost
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