Chip costs are exploding because of design complexity Bluespec 1 Design Affects Everything Issues Found on First Spin ICs ASICs 0 Arvind Computer Science Artificial Intelligence Lab Massachusetts Institute of Technology C ost M 25 Prototype Validation 20 Verification 10 Architecture 0 13 m Silicon Feature Dimension L07 1 Common quotes February 24 2006 90nm wSource IBM IBS Inc L07 2 http csg csail mit edu 6 375 Make Inspect Rework De fec t Defect Almost complete reliance on post design verification for quality http csg csail mit edu 6 375 20 17 14 12 11 11 10 10 7 4 3 The U S auto industry Sought quality solely through post build inspection Planned for defects and rework Verification is a problem Timing closure is a problem Physical design is a problem M 50 43 Through the early 1980s Design is not a problem design is easy t se d in February 24 2006 40 and U S quality was L07 3 February 24 2006 http csg csail mit edu 6 375 Defect http csg csail mit edu 6 375 30 Design and verification dominate escalating project costs Physical 15 0 0 18 m 20 wSource Aart de Geus CEO of Synopsys wBased on a survey of 2000 users by Synopsys IC Design Costs 30 5 February 24 2006 Functional Logic Error Analog Tuning Issue Signal Integrity Issue Clock Scheme Error Reliability Issue Mixed Signal Problem Too Much Power Has Path s Too Slow Has Path s Too Fast IR Drop Issues Firmware Error Other SoC failures costing time spins 10 L07 4 New mind set less than world class Design affects everything A good design methodology Adding quality inspectors verification engineers and giving them better tools was not the solution The Japanese auto industry showed the way It is essential to Design for Correctness Zero defect manufacturing February 24 2006 L07 5 http csg csail mit edu 6 375 New semantics for expressing behavior to reduce design complexity Decentralize complexity Rule based Let us think about one rule at a time Formalize composition Modules with RTL has poor semantics for composition data in data out push req n full pop req n empty clk rstn These constraints are spread over many pages of the documentation Bluespec http csg csail mit edu 6 375 L07 6 http csg csail mit edu 6 375 ch f su l e o n ib atios feas c i f i i ver aints e n r ch i o n s t a c m l No orma i nf guarded interfaces Automatically manage and ensure the correctness of connectivity i e correct byconstruction methodology Retain resilience to changes in design or layout e g compute latency s Promote regularity of layout at macro level February 24 2006 February 24 2006 Example Commercially available FIFO IP block specifications Guarded Atomic Actions Can keep up with changing specs Permits architectural exploration Facilitates verification and debugging Eases changes for timing closure Eases changes for physical design Promotes reuse L07 7 February 24 2006 http csg csail mit edu 6 375 L07 8 Bluespec promotes composition through guarded interfaces theModuleA Enqueue arbitration control theFifo deq value2 theFifo first enab not empty not empty theFifo deq value4 theFifo first February 24 2006 FIFO rdy n theFifo enq value3 Power to express complex static structures and constraints rdy deq theModuleB enq enab not full In Bluespec SystemVerilog BSV The compiler generates the necessary hardware muxing and control Micro protocols need less or no verification Easier to make changes while preserving correctness rdy Dequeue arbitration control http csg csail mit edu 6 375 Checked by the compiler Micro protocols are managed by the compiler theFifo n first theFifo enq value1 Self documenting interfaces Automatic generation of logic to eliminate conflicts in use Smaller simpler clearer more correct code L07 9 Bluespec State and Rules organized into modules February 24 2006 http csg csail mit edu 6 375 L07 10 Examples module GCD Multiplication IP Lookup interface All state e g Registers FIFOs RAMs is explicit Behavior is expressed in terms of atomic actions on the state Rule condition action Rules can manipulate state in other modules only via their interfaces February 24 2006 http csg csail mit edu 6 375 L07 11 February 24 2006 http csg csail mit edu 6 375 L07 12 Programming with rules A simple example GCD in BSV 6 6 y swap sub module mkGCD I GCD Reg int x mkRegU Reg int y mkReg 0 Euclid s algorithm for computing the Greatest Common Divisor GCD 15 9 x rule swap x y y 0 x y y x endrule rule subtract x y y 0 y y x endrule subtract method Action start int a int b if y 0 x a y b endmethod method int result if y 0 return x endmethod endmodule February 24 2006 http csg csail mit edu 6 375 L07 13 int y 0 rdy start module mkGCD I GCD Reg int x mkRegU Reg int y mkReg 0 GCD module y 0 result implicit conditions enab rdy L07 14 Combine swap and subtract rule method Action start int a int b if y 0 x a y b endmethod method int result if y 0 return x endmethod Does it compute faster endmodule The module can easily be made polymorphic Many different implementations can provide the same interface module mkGCD I GCD http csg csail mit edu 6 375 Assumes x 0 and y 0 rule swapANDsub x y y 0 x y y x y endrule rule subtract x y y 0 y y x endrule interface I GCD method Action start int a int b method int result endinterface February 24 2006 http csg csail mit edu 6 375 GCD Another implementation GCD Hardware Module int int February 24 2006 L07 15 February 24 2006 http csg csail mit edu 6 375 L07 16 Generated Verilog RTL Bluespec Tool flow Bluespec SystemVerilog source Bluespec Compiler Verilog 95 RTL Bluespec C sim Verilog sim Cycle Accurate VCD output Legend gates Debussy Visualization files Bluespec tools 3rd party tools February 24 2006 RTL synthesis L07 17 http csg csail mit edu 6 375 Generated Hardware x en x y en 0 February 24 2006 Generated Hardware Module x y wen rdy y sub swap subtract http csg csail mit edu 6 375 start en start en x en x x rdy February 24 2006 L07 18 http csg csail mit edu 6 375 start C module mkGCD CLK RST N start a start b EN start RDY start result RDY result input CLK input RST N action method start input 31 0 start a input 31 0 start b input EN start output RDY start value method result output 31 0 result output RDY result register x and y reg 31 0 x wire 31 0 x D IN wire x EN reg 31 0 y wire 31 0 y D IN wire y EN rule RL subtract assign WILL FIRE RL subtract x SLE y d3 y EQ 0 d10 rule RL swap assign WILL FIRE RL swap x SLE y d3 y EQ …
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