Verilog 2 Design Examples 6 375 Complex Digital Systems February 12 2007 Course administrative notes If you did not receive an email over the weekend concerning the course then you are not on the student mailing list please email 6 375 staff Lab 1 is due Friday February 16 2 stage SMIPSv2 processor RTL checked into CVS Critical thinking questions hardcopy due in class 6 375 Spring 2007 L03 Verilog 2 Design Examples 2 Verilog Design Examples Building blocks Greatest Common Divisor Unpipelined SMIPSv1 processor 6 375 Spring 2007 L03 Verilog 2 Design Examples 3 A module can be described in many different ways but it should not matter from outside Example mux4 mux4 Gate level structural Verilog module mux4 input a b c d input 1 0 sel output out wire 1 0 sel b not not0 sel b 0 sel 0 not not1 sel b 1 sel 1 wire n0 n1 n2 and and0 n0 c and and1 n1 a and and2 n2 d and and3 n3 b n3 sel 1 sel b 1 sel 1 sel b 1 b d a c sel 1 sel 0 wire x0 x1 nor nor0 x0 n0 n1 nor nor1 x1 n2 n3 wire y0 y1 or or0 y0 x0 sel 0 or or1 y1 x1 sel b 0 nand nand0 out y0 y1 endmodule out 6 375 Spring 2007 L03 Verilog 2 Design Examples 5 mux4 Using continuous assignments module mux4 input a b c d input 1 0 sel output out Language defined operators wire out t0 t1 assign t0 out sel 1 t0 sel 0 c sel 1 t1 sel 0 a assign t1 sel 1 d sel 1 b assign out t0 t0 sel 1 sel 0 c sel 1 t1 sel 0 a endmodule The order of these continuous assignment statements does not matter They essentially happen in parallel 6 375 Spring 2007 L03 Verilog 2 Design Examples 6 mux4 Behavioral style Four input multiplexer module mux4 input a b c d input 1 0 sel output out assign out sel sel sel sel 0 1 2 3 a b c d If input is undefined we want to propagate that information 1 bx endmodule 6 375 Spring 2007 L03 Verilog 2 Design Examples 7 mux4 Using always block module mux4 input a b c d input 1 0 sel output out reg out t0 t1 always a or b or c or d or sel begin t0 sel 1 c sel 1 a t1 sel 1 d sel 1 b out t0 sel 0 t1 sel 0 end endmodule The order of these procedural assignment statements does matter They essentially happen sequentially 6 375 Spring 2007 L03 Verilog 2 Design Examples 8 mux4 Always block permit more advanced sequential idioms module mux4 input a b c d input 1 0 sel output out module mux4 input a b c d input 1 0 sel output out reg out reg out always begin if sel 2 d0 out a else if sel out b else if sel out c else if sel out d else out 1 bx end always begin case sel 2 d0 out a 2 d1 out b 2 d2 out c 2 d3 out d default out 1 bx endcase end endmodule 2 d1 2 d2 2 d3 endmodule Typically we will use always blocks only to describe sequential circuits 6 375 Spring 2007 L03 Verilog 2 Design Examples 9 Parameterized mux4 module mux4 parameter WIDTH 1 input WIDTH 1 0 module mux4 input a b c da b c d input input 1 0 1 0 sel sel output WIDTH 1 0 out output out default value wire out t0 t1 wire WIDTH 1 0 out t0 t1 assign out t0 sel 0 t1 sel 0 assign c a assignt0t1 sel 1 sel 1 d sel 1 b assign d b assignt1t0 sel 1 sel 1 c sel 1 a assign out sel 0 t0 t1 Instantiation Syntax endmodule endmodule Parameterization is a good practice for reusable modules mux4 32 alu mux a op1 b op2 c op3 d op4 sel alu mux sel out alu mux out 6 375 Spring 2007 L03 Verilog 2 Design Examples 10 flip flops module FF0 input clk input output q always posedge clk begin q d end endmodule d module FF input clk input d input en output q always posedge clk begin if en q d end endmodule next X clk next X clk X Q D D Q X enable 6 375 Spring 2007 L03 Verilog 2 Design Examples 11 flip flops with reset always posedge clk begin if resetN Q 0 else if enable Q D end synchronous reset always posedge clk or next X clk D resetN Q X enable What is the difference negedge resetN begin if resetN Q 0 else if enable reset asynchronous Q D 6 375 Spring 2007 L03 Verilog 2 Design Examples 12 Register module register parameter WIDTH 1 input clk input WIDTH 1 0 d input en output WIDTH 1 0 q always posedge clk begin if en q d end endmodule 6 375 Spring 2007 L03 Verilog 2 Design Examples 13 Register in terms of Flipflops module register2 input clk input 1 0 d input en output 1 0 q module register2 input clk input 1 0 d input en output 1 0 q always posedge clk begin if en q d end endmodule FF ff0 clk clk d d 0 en en q q 0 FF ff1 clk clk d d 1 en en q q 1 endmodule Do they behave the same yes 6 375 Spring 2007 L03 Verilog 2 Design Examples 14 Static Elaboration Generate module register parameter WIDTH 1 input clk input WIDTH 1 0 d genvars disappear after static input en elaboration output WIDTH 1 0 q Generated names will have genvar i regE i prefix generate for i 0 i WIDTH i i 1 begin regE FF ff clk clk d d i en en q q i end endgenerate endmodule 6 375 Spring 2007 L03 Verilog 2 Design Examples 15 Verilog Design Examples Building blocks Greatest Common Divisor Unpipelined SMIPSv1 processor 6 375 Spring 2007 L03 Verilog 2 Design Examples 16 GCD in C int GCD int inA int inB int done 0 int A inA int B inB while done if A B swap A A B B swap else if B 0 A A B else done 1 Such a GCD description can be easily written in Behavioral Verilog It can be simulated but it will have nothing to do with hardware i e it won t synthesize return A 6 375 Spring 2007 L03 Verilog 2 Design Examples 17 Behavioral GCD in Verilog module gcdGCDUnit behav parameter W 16 input W 1 0 inA inB output W 1 0 out reg W 1 0 A B out swap integer done always begin done 0 A inA B inB while done begin if A B swap A A B B swap else if B 0 A A B else done 1 end User simply sets the input operands and checks the output the answer …
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