INVITED PAPER Lithography and Other Patterning Techniques for Future Electronics As integrated circuits continue to go smaller laying down circuit patterns on semiconductor material becomes more expensive and new techniques are needed By R Fabian Pease Fellow IEEE and Stephen Y Chou Fellow IEEE ABSTRACT For all technologies from flint arrowheads to DNA making and for directly writing on the wafer also known as microarrays patterning the functional material is crucial For Bmaskless lithography Going from laboratory demonstra semiconductor integrated circuits ICs it is even more critical tion to manufacturing technology is enormously expensive than for most technologies because enormous benefits accrue to going smaller notably higher speed and much less energy 9 1 billion and for good reason Just in terms of data rate mask pattern to resist pattern today s exposure tools achieve consumed per computing function The consensus is that ICs about 10 Tb s at an allowable error rate of about 1 h this data will continue to be manufactured until at least the B22 nm node rate will double with each generation In addition the edge the linewidth of an equal line space pattern Most patterning placement precision required will soon be 30 parts per billion of ICs takes place on the wafer in two steps a lithography the There are so many opportunities for unacceptable perfor patterning of a resist film on top of the functional material and mance that making the right decision goes far beyond under b transferring the resist pattern into the functional material standing the underlying physical principles But the benefits of usually by etching Here we concentrate on lithography Optics has continued to be the chosen lithographic route despite its continuing to be able to manufacture electronics at the 22 nm node and beyond appear to justify the investment and there is continually forecast demise A combination of 193 nm radia no shortage of ideas on how to accomplish this tion immersion optics and computer intensive resolution and 32 nm nodes Optical lithography usually requires that we KEYWORDS Electron beam lithography imprint lithography ion beam lithography laser beam lithography lithography first make a mask and then project the mask pattern onto a nanofabrication nanoimprint nanotechnology patterning resist coated wafer Making a qualified mask although origi phase separation photolithography self assembly enhancement technology will probably be used for the 45 nally dismissed as a Bsupport technology now represents a significant fraction of the total cost of patterning an IC largely because of the measures needed to push resolution so far beyond the normal limit of optical resolution Thus although optics has demonstrated features well below 22 nm it is not clear that optics will be the most economical in this range nanometer scale mechanical printing is a strong contender extreme ultraviolet is still the official front runner and electron beam lithography which has demonstrated minimum features less than 10 nm wide continues to be developed both for mask Manuscript received April 18 2007 revised October 2 2007 This work was supported by the DARPA Advanced Lithography Program R F Pease is with Stanford University Stanford CA 94305 USA S Y Chou is with Princeton University Princeton NJ 08544 USA Digital Object Identifier 10 1109 JPROC 2007 911853 248 Proceedings of the IEEE Vol 96 No 2 February 2008 I DRIVING FORCES I N PATTERNING In the past 40 years the minimum dimension of integrated circuits ICs has been shrinking at a rate of 30 smaller feature size every three years following the so called Moore s law The International Technology Roadmap for Semiconductors ITRS an industrial consensus of future technology largely based on Moore s law is a 100 page document that suggests that features of complementary metal oxide semiconductor MOS circuitry will continue to shrink down to at least the B22 nm node 38 At that node the half of the center to center pitch of first level of interconnect is 22 nm and the width of the resist feature for the gate electrode is 15 nm the etched gate electrode is even smaller about 9 nm Fig 1 0018 9219 25 00 2008 IEEE Pease and Chou Lithography and Other Patterning Techniques for Future Electronics Fig 1 Experimental example of results achieved with a combination of phase shifting mask imaging and etch slimming showing gate lengths down to 9 nm 17 a Fully depleted silicon on isulator SOI MOS field effect transistors FETs with sub 10 nm SOI channel thickness b Same chromeless phase shift mask used for all three devices dose varied A 1999 vintage 248 nm stepper NA 0 6 Canon EX 4 c Etch bias used as well There is very good reason for this continued drive to shrink dimensions Until recently scaling down all linear dimensions L along with applied voltages led to a proportionate increase in speed and a reduction in energy per computing function to L 3 Although the former advantage is the most frequently touted the latter is probably the more significant even more so as electronics increasingly will be hand carried Although the classical scaling laws 1 74 75 may not apply quantitatively as we continue to scale down dimensions it appears that we will get more computing per unit time and per unit energy Scaling to 22 nm will bring advantages in terms of energy per computing function as well as speed There may be other ways to reduce power per computing function For example just about all transistors operate by modulating the height of a thermal barrier Thence it follows that to change the current tenfold at room temperature the change in voltage applied to the control electrode must be at least 60 mV in current jargon we say that we need 60 mV decade 2 But as we scale down dimensions we must also scale down signal and supply voltages to avoid breakdown Thus at finer dimensions the current in transistors that are Boff will become appreciable and will increase the dissipated power Some newer devices operate on different principles and may well not suffer this problem These and other exotic devices e g spintronics 3 and strategies e g three dimensional 3 D integrated circuitry and quantum computing1 are being pursued and are described elsewhere as well as in separate papers in this issue But even with these exotic devices and structures the power and speed advantages of scaling down dimensions remain and compel us to invest in appropriate patterning technologies At least one
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