EE143 F05 Lecture 26 Sealing of Cavities Deposition Professor N Cheung U C Berkeley Thermal Oxidation 1 EE143 F05 Lecture 26 Deep Reactive Ion Etching Uses high density plasma to alternatively etch silicon and deposit an etch resistant polymer on side walls Polymer Polymer deposition Professor N Cheung U C Berkeley Silicon etch using SF6 chemistry 2 EE143 F05 Lecture 26 Use of SOI for MEMS Process oxide mask layer Si device layer 20 m thick 1 Begin with a bonded SOI wafer Grow and etch a thin thermal oxide layer to act as a mask for the silicon etch 2 Etch the silicon device layer to expose the buried oxide layer buried oxide layer Si handle wafer silicon Thermal oxide 3 Etch the buried oxide layer in buffered HF to release free standing structures Professor N Cheung U C Berkeley 3 EE143 F05 Lecture 26 Molding Example LIGA Process Lithographie Galvanoformung Abformung Lithography electroplating and molding processes to produce microstructures Metal plating Plastic molding Very thick resist Final microstructure Professor N Cheung U C Berkeley 4 EE143 F05 Lecture 26 SCREAM Process Question Why 2nd Si etch Al electrodes Professor N Cheung U C Berkeley 5 EE143 F05 Lecture 26 Capacitive sensors Typically used to measure displacement C 0 A d Area A Separation d Example Pressure Transducer Professor N Cheung U C Berkeley C x C x P 6 EE143 F05 Lecture 26 Example of Thermal Bimorph Actuator gold 14 x 10 6 oC Professor N Cheung U C Berkeley Si 2 6 x 10 6 oC 7 EE143 F05 Lecture 26 Process Flow of Micro tweezers by selective CVD Tungsten 0 volts open Professor N Cheung U C Berkeley 15 volts closed 8 EE143 F05 Professor N Cheung U C Berkeley Lecture 26 9 EE143 F05 Lecture 26 Example Lateral Resonator Professor N Cheung U C Berkeley 10 EE143 F05 Lecture 26 Paschen Curve for gas breakdown Using electrostatic actuator convenient voltage is limited to 200V Professor N Cheung U C Berkeley 11 EE143 F05 Lecture 26 Electrostatic Gated Pneumatic Valve Professor N Cheung U C Berkeley 12 EE143 F05 Lecture 26 Process Flow of Electrostatic Gated Pneumatic Valve Professor N Cheung U C Berkeley 13 EE143 F05 DNA analysis in Microchannels Stretching DNA and sequencing Cao et al Princeton Lecture 26 Entropic trap Han Craighead Cornell MIT 75nm 30 m 30 m Professor N Cheung U C Berkeley 14 EE143 F05 Lecture 26 Optical observation of single molecules in their natural state Cornell Univ Light impeding Al holes Zero mode waveguides Professor N Cheung U C Berkeley 15 EE143 F05 Linking Si Technology with Biology Lecture 26 Snail neuron grown atop an Infineon Technologies CMOS device that measures the neuron s electrical activity linking chips and living cells Source Max Planck Institute Professor N Cheung U C Berkeley 16 EE143 F05 Lecture 26 Responsive Drug Delivery Systtem Professor N Cheung U C Berkeley Source Madou Lab Chip 3 26 28N 2003 17 EE143 F05 Lecture 26 Multi Structural Layer MEMS Technology Multiple structural layers allow for more complex devices 1 layer sensors 2 layers simple actuators gears mirrors 3 layers advanced actuators with linkages Example Sandia Multi level MEMS Technology SUMMiT 4 level poly Si surface micromachining process 1 ground plane electrical interconnect 3 mechanical layers Cross sectional SEM of MEMS gear Professor N Cheung U C Berkeley 18 EE143 F05 Lecture 26 Monolithic MEMS IC Integration Approaches Interleaved process Processing steps for MEMS and IC are interleaved in the process flow Modular process Allows for separate development optimization of MEMS and electronics components Use of IC and or MEMS foundries a possibility Professor N Cheung U C Berkeley 19 EE143 F05 Lecture 26 Challenges of Modular processes MEMS first Approach Topography is an issue Degradation of MEMS devices during hightemperature IC process steps Electronics must be protected during HF release etch IC first Approach MEMS must be low temperature process Electronics must be protected during HF release etch Professor N Cheung U C Berkeley 20 EE143 F05 Lecture 26 Interleaved Process Example Analog Devices Inc Metallization process steps performed last Performance of MEMS and electronics compromised Professor N Cheung U C Berkeley 21 EE143 F05 Lecture 26 MEMS first Process Example Sandia National Lab MEMS fabricated in 12 m deep trench Filled with SiO2 and planarized using CMP Modular process but IC foundries wary Professor N Cheung U C Berkeley 22 EE143 F05 Lecture 26 MEMS Last Process Example UC Berkeley Non standard refractory W metallization melting point 3000oC IC foundries not interested Professor N Cheung U C Berkeley 23 EE143 F05 Lecture 26 New MEMS Last Technology A Franke UC Berkeley Standard CMOS process Al based metallization Poly SiGe as structural material processing temperatures 500 C possible Amorphous Si protects CMOS during HF release etch Professor N Cheung U C Berkeley 24 EE143 F05 Lecture 26 MEMS Technology Developments Trends Challenges Residual stress Topography Heterogeneous integration More structural layers poly Si MEMS Thick multilayer structural films Silicon on Insulator Uniform thickness and reproducible mechanical properties of Si Buried Oxide is excellent etch stop Buried oxide is transparent waveguide optical coupling Further reading on MEMS http mems isi edu http www bsac eecs berkeley edu sunil EE245 index htm Professor N Cheung U C Berkeley 25 EE143 F05 Lecture 26 Heterogeneous Integration of Microsystems Professor Nathan Cheung EECS For reference only BioMEMS Emitters Filter Detectors GeOI Green LED Si Ge high mobility electronics CPU Blue LED MOS IC III V Encapsulated battery with switch LED 5mm 200 m Micro LED display pump Laser Array Laser Emitter Arrays Photonics on Si Optical Micro mirrors Modulator Micro fluidic channels InGaN LEDs on Si Encapsulated Power source 1 m Professor N Cheung U C Berkeley Si microfluidic channels 200 m 26
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