EE143 F2010 Lecture 20 Importance of Layer to Layer Alignment Example metal line to contact hole marginal contact no contact Example of Design Rule If the minimum feature size is 2l then the safety margin for overlay error is l safety margin to allow for misalignment Design Rules are needed Interface between designer process engineer Guidelines for designing masks Professor N Cheung U C Berkeley EE143 F2010 Lecture 20 IC RESISTOR MASK LAYOUTS REGISTRATION OF EACH MASK Registration of mask patterns is critical show separate layouts to avoid ambiguity Oxide mask dark field Contact mask dark field Al mask clear field B registration shows overlay of patterns 0 A A 1 2 scale in m for B B cut B Registration of one mask to the next also called alignment and overlay is a crucial aspect of lithography Professor N Cheung U C Berkeley EE143 F2010 Lecture 20 Same Layout but with misregistration misalignment B perfect registration 0 A A 1 2 scale in m for B B cut B B Contact mask misaligned by 2 m 0 A A 1 2 scale in m for B B cut B Lets look again at cross section A A to understand the consequence of this misalignment Note contact mask 2 m Professor N Cheung U C Berkeley EE143 F2010 Lecture 20 Layout with no misregistration misalignment B perfect registration 0 A A 1 2 B Al A STEP 7 Professor N Cheung U C Berkeley p type layer A EE143 F2010 Lecture 20 Layout with misregistration misalignment B Contact mask misaligned by 2 m 0 A A 1 2 scale in m for B B cut B Al Al A p type layer This resistor has an open circuit A STEP 7 Thus we need safety margins in layout which take into account the possible tolerances in fabrication Each process has a set of design rules which specify the safety margins Professor N Cheung U C Berkeley EE143 F2010 Lecture 20 Layout Design Rules 1 Absolute Value Design Rules Use absolute distances 2 l based Design Rules Professor N Cheung U C Berkeley 6 6 EE143 F2010 Lecture 20 EE143 Layout Design Rules 1 Basic length unit l 2 m 1 1 Lithography and etching limit 2l 1 2 Overlay accuracy l Professor N Cheung U C Berkeley 7 EE143 F2010 Lecture 20 2 1 Metal Si Contact Hole same rule for Metal poly 2l 2l Min contact hole 2 l x 2 l l l Min contact hole to diffusion layer distance l l n Al SiO2 p sub Professor N Cheung U C Berkeley n SiO2 p sub 8 EE143 F2010 Lecture 20 2 2 Metal Lines Min width 2l Min metal metal spacing 3l Rationale Line 1 3l 2l Line 2 metal runs on rough topography 3 l spacing to ensure no shorting between the 2 lines Professor N Cheung U C Berkeley 9 EE143 F2010 Lecture 20 Min overlap of contact hole l l l l SiO2 Etching problem CVD SiO2 deposition problem in narrow gap Si Professor N Cheung U C Berkeley 10 EE143 F2010 Lecture 20 Metal line width is larger when running over a contact hole l 2l 2l 4l Configuration 1 l l Configuration 2 2l l Professor N Cheung U C Berkeley 11 EE143 F2010 Lecture 20 2 3 Poly Si Lines Min width 2l 2l Line 1 2l Min poly poly spacing 2 l Line 2 Rationale Unlike metal lines poly Si runs on smoother topography metal l poly l Min underlap of metal poly contact l 4l 4l Professor N Cheung U C Berkeley 12 EE143 F2010 Lecture 20 Example Metal Contact to Poly metal l l poly Note Both metal and poly linewidths will enlarge to accommodate contact hole overlay error l Professor N Cheung U C Berkeley 13 EE143 F2010 Lecture 20 2 4 MOS Thin Oxide Region Thick Oxide Region FOX Min Width 2 l 2l Thin Oxide Region active device area 2l Min spacing 3 l 3l 2l Professor N Cheung U C Berkeley 14 EE143 F2010 Lecture 20 Min underlap of thin oxide contact l l l Professor N Cheung U C Berkeley 15 EE143 F2010 Lecture 20 3 Poly Si Gate Min gate overlap of field oxide 2l 2l Comment Avoid n channel formation during S D Implant n n n ideal With overlay error Professor N Cheung U C Berkeley 16 EE143 F2010 Lecture 20 Min thin oxide contact to gate spacing 2 l 2l Professor N Cheung U C Berkeley 2l 17 EE143 F2010 Lecture 20 Comment Al to poly contact should not be directly on top of gate oxide area Al Poly gate Gate oxide Si Al Poly Al 400OC Al spike Poly SiO2 SiO2 Si Si Professor N Cheung U C Berkeley 18 EE143 F2010 Lecture 20 Al contact on thick oxide area ok 2l SiO2 CVD FOX Professor N Cheung U C Berkeley 19 EE143 F2010 Min Gate Width 2 l Min Gate Length 2 l Lecture 20 Usually W L are specified by circuit requirement Min poly to thin oxide spacing l l Professor N Cheung U C Berkeley 20 EE143 F2010 Example Lecture 20 Design a minimum size poly gate MOS transistor with W L 4 m 4 m 2 l x 2l Half way distance to next MOSFET 1 5 l Minimum size contact 2lx2l Minimum thin oxide region underlap of contact l Minimum source drain contact to gate spacing 2l Minimum L 2l Minimum W 2l Minimum gate overlap of field oxide region 2l Minimum metal overlap of contact l Minimum thin oxide region to thin oxide region spacing 3l Layout area transistor 15lx7l 105 l2 Professor N Cheung U C Berkeley metal poly Active region Contact hole 21
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