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Berkeley ELENG 143 - Importance of Layer-to-Layer Alignment

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Professor N Cheung, U.C. BerkeleyLecture 20EE143 F2010Importance of Layer-to-Layer Alignment marginal contact Design Rules are needed:• Interface between designer & process engineer• Guidelines for designing masksExample of Design Rule:If the minimum feature size is 2l, then the safety margin for overlay error is l.Example: metal line to contact hole no contact!safety margin to allow for misalignmentProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010IC RESISTOR MASK LAYOUTS – REGISTRATION OF EACH MASK Registration of mask patterns is critical  show separate layouts to avoid ambiguityOxide mask (dark field)Al mask (clear field)Contact mask (dark field)A ABB012“registration” shows overlay of patternsscale in m for B-B “cut”Registration of one mask to the next (also called “alignment” and “overlay”) is a crucial aspect of lithographyProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010Same Layout but with misregistration (misalignment)perfect registrationA ABB012scale in m for B-B “cut”A ABB012scale in m for B-B “cut”Contact mask misaligned by 2mLets look again at cross-section A-A to understand the consequence of this misalignment. Note contact mask 2mProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010Layout with no misregistration (misalignment)perfect registrationA ABB012AASTEP 7Alp-type layerProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010Layout with misregistration (misalignment)A ABB012scale in m for B-B “cut”Contact mask misaligned by 2mThus we need safety margins in layout which take into account the possible tolerances in fabrication. Each process has a set of “design rules” which specify the safety margins.This resistor has an open circuit !!AASTEP 7Alp-type layerAlProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F20106Layout Design Rules(1) Absolute-Value Design Rules* Use absolute distances (2) l -based Design Rules6Professor N Cheung, U.C. BerkeleyLecture 20EE143 F20107EE143 Layout Design Rules1. Basic length unit = l = 2m1.2 Overlay accuracy = l1.1 Lithography and etching limit =2lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201082.1 Metal-Si Contact Holel2llMin. contact hole = 2 l x 2 ll2Min contact hole to diffusionlayer distance = ln+p-subSiO2n+p-subSiO2Al(same rule for Metal-poly)lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201092.2. Metal LinesMin. metal-metalspacing = 3ll3l2Line2Line1[Rationale]metal runs on rough topography3 l spacing to ensure no shorting between the 2 lines.Min width = 2lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201010Min overlap of contact hole = lllSiEtchingproblemCVD SiO2deposition.problem innarrow gaplSiO2Professor N Cheung, U.C. BerkeleyLecture 20EE143 F201011Metal line-width is larger when runningover a contact holell2ll4l22lllConfiguration 1Configuration 2Professor N Cheung, U.C. BerkeleyLecture 20EE143 F2010122.3 Poly-Si LinesMin width = 2lMin poly-poly spacing = 2 lMin underlap of metal/poly contact = ll2l2Line 2llll44 polymetalLine 1[Rationale: Unlike metal lines, poly-Si runs on smoother topography]Professor N Cheung, U.C. BerkeleyLecture 20EE143 F201013llpolymetalExample: Metal Contact to PolyNote:Both metal and poly linewidthswill enlarge to accommodatecontact hole overlay error lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010142.4. MOS Thin-Oxide RegionMin spacing = 3 lThick Oxide Region (FOX)Thin Oxide Region(active device area)l2l2l2l3Min Width = 2 lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201015Min underlap of thin-oxide contact = lllProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F2010163. Poly-Si Gaten+n+n+Min gate-overlap offield oxide =l2[Comment]l2Avoid n+ channel formation during S/D ImplantidealWith overlay errorProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201017Min thin-oxide contact to gate spacing = 2 l2 l2 lProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201018AlPolySiO2Si~400OCAlPolySiO2SiAlspikeAlPoly gateComment:Al to poly contactshould not be directly on topof gate oxide areaSiGate oxideProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201019SiO2 (CVD)FOXl2Al contact on thick oxide area okProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201020Min Gate Width = 2 lMin Gate Length = 2 lUsually: W/L are specified by circuit requirement.Min. poly to thin oxide spacing = llProfessor N Cheung, U.C. BerkeleyLecture 20EE143 F201021Design a minimum-size poly-gate MOS transistor with W/L = 4m/4m (2 l x 2l )ExampleMinimum size contact = 2lx2lMinimum thin-oxide-region underlap of contact = lMinimum source/drain contact to gate spacing = 2lMinimum L = 2l Minimum W = 2lMinimum gate overlap of field-oxide region = 2lMinimum metal overlap of contact = lMinimum thin-oxide-region to thin-oxide-region spacing = 3l* Layout area /transistor = 15lx7l = 105 l2metalpolyActive regionContact holeHalf-waydistance tonext MOSFET( = 1. 5 l


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Berkeley ELENG 143 - Importance of Layer-to-Layer Alignment

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