EE143 F05 Lecture 20 Process Integration Self aligned Techniques LOCOS self aligned channel stop Self aligned Source Drain Lightly Doped Drain LDD Self aligned silicide SALICIDE Self aligned oxide gap MEMS Release Techniques Sacrificial Layer Removal Substrate Undercut Example IC Process Flows NMOS Generic NMOS Process Flow CMOS The MOSIS Process Flow Advance MOS Techniques Twin Well CMOS Retrograde Wells SOI CMOS Professor N Cheung U C Berkeley 1 EE143 F05 Lecture 20 Self aligned channel stop with Local Oxidation LOCOS LOCOS Process Flow Si3N4 CVD pad oxide Si Professor N Cheung U C Berkeley 2 EE143 F05 Lecture 20 B channel stop implant dose 1013 cm2 B Si thermal oxidation high temperature FOX p Professor N Cheung U C Berkeley p Self aligned channel stop 3 EE143 F05 Lecture 20 Comment Channel Inversion If poly or metal lines lie on top of the FOX they will form a parasitic MOS structure If these lines carrying a high voltage they may create an inversion layer of free electrons at the Si substrate and shorts out neighboring devices The relatively highly doped Si underneath the channel stop raises the threshold voltage needed for the inversion metal Device 1 Device 2 SiO2 Electron Inversion Layer Professor N Cheung U C Berkeley p Si 4 EE143 F05 Lecture 20 Comments Non self aligned alternative B 2 1 P R SiO2 P P 3 SiO2 P Si P Disadvantages 1 Two lithography steps 2 Channel stop doping not FOX aligned Professor N Cheung U C Berkeley 5 EE143 F05 Lecture 20 Self aligned Source and Drain As poly Si gate Perfect Alignment n n As Off Alignment n n The n S D always follows gate Professor N Cheung U C Berkeley 6 EE143 F05 Lecture 20 Comment Non self aligned Alternative n n n n 1 2 Channel not linked to S D n n Solution Use gate overlap to avoid offset error Stray capacitance Disadvantages Two lithography steps excess gate overlap capacitance Professor N Cheung U C Berkeley 7 EE143 F05 Lecture 20 Lightly Doped Drain LDD LDD 1E17 to 1E18 cm3 Professor N Cheung U C Berkeley 8 EE143 F05 Lecture 20 Lightly Doped Source Drain MOSFET LDD CVD oxide spacer n n n n SiO2 p sub The n pockets LDD doped to medium conc 1E18 are used to smear out the strong E field between the channel and heavily doped n S D in order to reduce hot carrier generation Professor N Cheung U C Berkeley 9 EE143 F05 Lecture 20 LDD Process Flow using Ion Implantation n implant for LDD CVD conformal deposition SiO2 CVD SiO2 SiO2 Professor N Cheung U C Berkeley Directional RIE of CVD Oxide 10 EE143 F05 Lecture 20 Spacer left when CVD SiO2 is just cleared on flat region 0 25 m 0 05 m n n n implant n Professor N Cheung U C Berkeley n n n 11 EE143 F05 Lecture 20 Self Aligned Silicide Process SALICIDE using Ion Implantation and Metal Si reaction poly gate n TiSi2 metal n Metal silicides are metallic They lower the sheet resistance of S D and the poly gate Professor N Cheung U C Berkeley 12 EE143 F05 Lecture 20 SALICIDE Process Flow oxide spacer n Professor N Cheung U C Berkeley n SiO2 13 EE143 F05 Lecture 20 Ti deposition Ti n n SiO2 Si Ti TiSi2 Ti Ti heat treatment 700o C Ti 2 Si TiSi2 Ti will not react with SiO2 Selective etch to remove unreacted Ti only Professor N Cheung U C Berkeley 14 EE143 F05 Lecture 20 Self aligned Oxide Gap DRAM structure MOSFET with a capacitor Thermal Oxide grown conformal on poly I small oxide spacing 30nm poly II poly I Gate oxide n substrate poly I MOSFET Professor N Cheung U C Berkeley For a small spacing between poly I and polyII inversion charges between MOSFET and Capacitor are electrically linked No need for a separate n island inversion charge layer MOS Capacitor poly II V plate 15 EE143 F05 Lecture 20 Process Flow of MEMS Rotating Mechanisms In Plane Movement Micro turbine Engine Professor N Cheung U C Berkeley 16 EE143 F05 Lecture 20 Process Flow for a Hinge Structure Out of plane Movement Professor N Cheung U C Berkeley 17 EE143 F05 Lecture 20 Layout of Thermal Bimorph Actuator See 143 Lab Manual for details Professor N Cheung U C Berkeley 18 EE143 F05 Lecture 20 After Patterning Poly Si Mask 2 Top View Aluminum Poly Si Oxide Si substrate Al Poly contact Cross Section Professor N Cheung U C Berkeley 19 EE143 F05 Lecture 20 After Patterning Intermediate Oxide Mask 3 Contact Hole Cut Top View Aluminum Poly Si Oxide Si substrate Al Poly contact Cross Section Professor N Cheung U C Berkeley 20 EE143 F05 Lecture 20 After Aluminum patterning Mask 4 To contact pad Top View Aluminum Poly Si Oxide Si substrate Al Poly contact Cross Section Professor N Cheung U C Berkeley 21 EE143 F05 Lecture 20 After XeF2 selective etching of Si Substrate Final Structure To contact pad Top View Aluminum Poly Si Oxide Si substrate Al Poly contact Cross Section Professor N Cheung U C Berkeley 22 EE143 F05 Lecture 20 A Generic NMOS Process Flow Substrate Boron doped 100 Si Resistivity 20 cm Thermal Oxidation 100 pad oxide CVD Si3N4 0 1 um Lithography Pattern Field Oxide Regions RIE removal of Nitride and pad oxide Channel Stop Implant 3x1012 B cm2 60keV Thermal Oxidation to grow 0 45um oxide Wet Etch Nitrdie and pad oxide Ion Implant for Threshold Voltage control 8x1011 B cm2 35keV Thermal Oxidation To grow 250 gate oxide LPCVD Poly Si 0 35um Dope Poly Si to n with Phosphorus Diffusion source Professor N Cheung U C Berkeley 23 EE143 F05 Lecture 20 A Generic NMOS Process Flow cont Lithography Poly Si Gate pattern RIE Poly Si gate Source Drain Implantation 1016 As cm2 80keV Thermal Oxidation Grow 0 1um oxide on poly Si And source drian LPCVD SiO2 0 35um Lithography Contact Window pattern RIE removal of CVD oxide and thermal oxide Sputter Deposit Al metal 0 7um Lithography Al interconnect pattern RIE etch of Al metallization Professor N Cheung U C Berkeley Sintering at 400oC in H2 ambient to improve contact resistance and to reduce oxide interface charge 24 EE143 F05 Lecture 20 NMOS Structure Generic NMOS Process Flow Boron doped Si 20 cm 100 Professor N Cheung U C Berkeley active device 5 m p Si 100 500 m 25 EE143 F05 Lecture 20 P R nitride SiO2 Si nitride P R SiO2 Si Professor N Cheung U C Berkeley B 3 1012 cm 2 60 keV 0 1 m 3 1017 cm3 26 EE143 F05 Lecture 20 Fox p p B 5 1011 cm2 35keV p Professor N Cheung U C Berkeley Fox p 27 EE143 F05 Lecture 20 As 80keV 1016 cm2 Resist n n Thermal oxide n Professor N Cheung U C Berkeley n 28 EE143 F05 Lecture 20 intermediate oxide Al CVD oxide n n Al H2 anneal 400oC Professor N Cheung U C Berkeley n n Si SiO2 Interface States Passivation 29
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